"Out of range" FVCO error on ADQ412

[constfang]

Hi, first of all, I'm totally newbie in FPGA so the solution to the following might be very very simple. I was having the first look at the ADQ412 data acquisition device with programmable FPGA, I was trying out the code provided by SPdevice and got this error:

ERROR:LIT:667 - Block 'MMCM_ADV symbol
"physical_group_framework_inst/sample_clk_manager_inst/sc_fb/framework_inst/sample_clk_manager_inst/SC_MMCM_ADV_inst"' has its target frequency, FVCO, out
of range. Valid FVCO range for speed grade "-1" is 600MHz - 1200MHz. The
computed FCVO is a function of the input frequency CLKIN1_PERIOD, the
division factor DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F attribute (FVCO =
1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The CLKIN_PERIOD
attribute may have been set by ngdbuild based on the user specified PERIOD
constraint. The current calculated FVCO is 1800.000180 MHz. Reference the V6
architecture Users Guide or search the Xilinx Answer Records database for the
error code.

As far as I know, this error comes from the exceeded FVCO value of the V6 FPGA, the problem is, "The current calculated FVCO is 1800.000180 MHz" seems to be correct since the ADQ412 is advertised to have a sampling rate of 1.8GHz. So what seems to be the problem here, is there anyway that I forgot to set the input clock to some external clock or something? Of course the one I should blame is SPDevice as I followed their instructions but still this error comes out.