Try a "preamble" of ramping the Vcc supply from zero to its
final value in (say) 1mS.
Very long timescales may not play well with the macromodel,
movement of nodes within a timestep may be less than the
tolerances.
The timing resistor values are very far from each other, I
know this is required to approach 50% duty but there's not
much room from 50% duty to outright fail (deadband exceeds
ramp amplitude). If you could tolerate (say) 45%/55% or even
more asymmetry, might try that out just to see if it's a
limits-of-functionality type problem.
You could also add a "kicker" current pulse at the beginning
of simulation to see if that's all it needs to get off the DC
solution point.