No.However, in some simulations (when more complex circuits are included; some logic gates, op-amps, and so on)
the jitter was simulated to tens of pico seconds.
Yes, use PSS+TDnoise.PSS+PNOISE can measure the absolute jitter.
vivekroy,
Yes I think so too.
However, in some simulations (when more complex circuits are included; some logic gates, op-amps, and so on) the jitter was simulated to tens of pico seconds.
It should be much smaller than the order, since the circuit is still in ideal condition and also the required design specification is around 10 ps.
ps jitter by simulation inaccuracy is not acceptable.
Would it be okay if I get a much smaller number through tightening reltol and abstol.
Thank you for your information.
It seems you still think numerical error as noise.then, is there an useful way to distinguish 'the real jitter' and 'simulation inaccuracy' if simulation is conducted in noisy condition?
Tighten “relref” and “maxstep”.In simulation 3-1, 3-2 of the first post, the oscillator frequency had been changed by a dummy signal.
How do you think about that?
It should also be solved, since I will use the signal for a specific period in later simulation.
Would it be possible to fix the problem by adjusting simulation parameters(maxstep, reltol, abstol...)?
What I meant was a transient simulation of osc whose output buffer is powered by a non-ideal power source (1 V + "noisy power").
The schematic consists of a 5 stage ring oscillator and an ideal voltage source of 1 V to power the osc.
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