Oscilations on half-bridge upper switch gate

[Georgiy_Klimov_]

Hello, dear collegues! I'm currently designing H-bridge converter for DC-motor drive.

I decided to use bootstrap driver for driving converter MOSFETs. IRF8721PBF were choosen as switches, IR2184 was chosen as a gate driver.
To quickly test their performance I soldered bread board with Half-bridge converter. You can see the circuitry on the figure. There is also decoupling capacitors on inputs of L7815(0,33uF ceramic) and IR2184(0,1uF ceramic).

The problem is the gate voltage drop on upper switch during switching on or it better to say oscilation on upper switch gate.
The oscillograms was pictured and you can see voltages on load, on upper and lower gates, and on Vboot and Vcc pins of IR2184.

I have tried different valiues of Cboot from 6.8nF to 1uF but there is no significant difference between results.
It would be great to get any suggestions concerning the problem.

Thanks

P.S.
I calculated Cboot according to equation from Design Tips "Using monolithic high voltage gate drivers" from Infeneon site.
Cboot=Qtot/dVbs=6.3nF;
Qtot=Qg+Qls+(Ilk_gs+Iqbs+Ilk+Ilk_diode+Ilk_cap+Ids)*Thon=26nC
dVbs=Vcc-Vf-Vgs_min-Vds=4.14V

Bootstrap diode was also choosen accoding to the DT mntioned below so that diode breakdown voltage was lower that DC bus voltage and it had low reverse recovery time (<100ns)

Bootstrap resistor was choosen basing on bootstrap circuit time constant Tboot. Tboot should be five times lower than the minimum time, when lower switch is on.

5*Tboot<1/f_sw*(1-DC); (f_sw - switching frequency, DC-maximum duty cycle)
Tboot<1/20000*(1-0.8);
Tboot<2us;

Tboot=Rboot*Cboot=>
=>Rboot<2us/6.8nC=295 Ohm plus I decided to add some margin, so I have R=235 Ohm

Qg=12nC; Total gate charge
Iqbs=150uA; % Floating section quiescent current
Ilk=50uA; % Floating section leakage current
Ids=0A; %Desat current
Qls=5nC; % Charge required by the internal level shifters
% level shift charge required per cycle (typically 5 nC for 500 V/600 V MGDs and 20 nC for
%1200 V MGDs)
Qp=4nC; % Сharge absorbed by the level shifter. QP is approximately 4 nC at VR = 50 V and increases to 7 nC as the rail voltage increases to 500 V
Qcmos=30nC; % QCMOS between 5 and 30 nC, depending on MGD.

Vcc=15V;
Vf=0.75V;
Vgs_min=10V;
Vds=0.1V;

 

[zenerbjt]

i suspect layout problem with fet drive.
I attach smps layout doc

--- Updated Jan 13, 2021 ---

It could be interesting to scope the half bridge point (switching node)..maybe that is ringing and going above the upper fet gate drive...causing the ON/OFF/ON

 

[Georgiy_Klimov_]

It could be interesting to scope the half bridge point (switching node)..maybe that is ringing and going above the upper fet gate drive...causing the ON/OFF/ON

I haven't understood, what point you want to scope? Do you mean the voltage between load and com? Could you please clarify it using attaced picture?

 

[FvM]

The first screenshot shows the oscillations of load (bridge center point) voltage exactly copied to the gate voltage. There's no additional oscillation in the gate circuit. Respectively it's no gate driver rather than a power circuit problem.

Possible reasons are either unstable 24 V supply, long cables without bypass capacitor near the bridge or other kinds of bad circuit layout.

Apparently not related to the problem, but 6.8 nF bootstrap capacitor looks inapproriately small. The calculation is for minimal, not for useful value. I won't go below 100 nF.

 

[dick_freebird]

I'd want a Cboot that's at least 10X the Cgg
of the driven FET, and that would result in a
>= -10% supply sag.

Now if your supply is at all marginal to the
high side UVLO threshold, you might flicker in
and out of lockout on each transition. It's
worth a look at the Cboot terminals with the
'scope in difference mode (or export .csv
of both and do the math) to see whether
you have adequate margin where you're
seeing this "behavior".

With extreme dV/dt you might also just be
seeing reference-ground artifacts from the
setup inductance as it sits, on the bench.
You might want another channel, all with
the same ground-point, looking at ground
and see if it's "busy" enough to want
de-embedding of the "ground signal" by
math or by difference-mode.

 

[KlausST]

Hi,

Does Cgg include miller capacitance?

I'd rather calculate with the gate charge that needs to be supplied by the bootstrap capacitor.

Or: There are good application notes with very detailed informations.

Klaus

 

[Easy peasy]

C1 is way too small - layout is very important - film foil caps right across the supply - right by the fets ....

 

[treez]

Scope the mid point of the power fets. Please show it here so we can advise you.
By mid-point i mean drain of bottom fet (source of top fet).

For security you can put a small schottky right at the chip, at the high side gate drive output. (to stop the high side gate drive going below the high side ground.