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[51] Oregano 8051 ip core tests on fpga

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mishaaal

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Oregano 8051 ip core test on fpga

has anybody here worked with the oregano systems 8051 ip core. I need help testing the parameterized number of timers on fpga. the lines from the user guide document are here:

"In the VHDL source file mc8051_p.vhd the constant C_IMPL_N_TMR can take
values from 1 to 256 to control this feature. Values out of this interval result in a non
functioning configuration of the core."


can someone explain how to access these new peripherals in the keil source code through the extended sfrs namely "TSEL and SSEL" that are created in the oregano 8051 IP core. the lines concerning are qouted here

To be able to reach all registers of the generated units without changing the address
space of the microcontroller only two 8bit registers are inferred as additional special
function registers. These are TSEL (address 0x8Eh for timer/counter units) and
SSEL (address 0x9Ah for serial interface units). If these registers point to a not
existent device number, the default unit number 1 is selected.
 

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