[SOLVED] Opto coupler for energy measurment ?

[KerimF]

Oh... so you don't have CD4000.lib, I asked you about it earlier I thought your silence meant you have it.
About LM339, I thought its model was loaded with LTspice libraries.

I will find the models of these ICs and post them here.

 

[crutschow]

The only reason to use an external analog multiplier is if you can't multiply the two digital values together in a microprocessor. The analog multiplier will have significantly poorer accuracy.

 

[KerimF]

The analog multiplier will have significantly poorer accuracy.

I am not familiar with multipliers, digital or analog.
Do you think a 0.3% accuracy is not good enough practically?
To be honest, I got this accuracy from simulation when I used comparators and gates (switching method). In my preliminary design, I avoided using transistors and/or diodes as it is the case with various logarithmic analog multipliers that should be implemented in integrated circuits to get adequate accuracy.

- - - Updated - - -

@ADGAN
The text below should be named as:
CD4000.lib

Please note that since this library is rather long, the CD4000.lib here is for 4001 and 4070 only.
I kept the file name as it is since it is written so in the schematic (asc) you received.

*=====================

* CD40xxx Model libraray for LTSPICE from www.linear.com/software

.SUBCKT CD40_IN_1 in out VDD VGND vdd3={vdd2} speed3={speed2} tripdt3={tripdt2}
* 3ns input delay
*.param Cval = 0.55e-12*4/({vdd3}-0.5)*{speed3}
* 10ns delay @5V
.param Cval = 1.8e-12*5/{vdd3}*{speed3}
.param vt1=0.5
.param gain=(1/{vdd3})
*
*D1 0 in CD40DIO1
*D2 in VDD CD40DIO1
R1 in out10 10k
C1 out10 VGND {Cval}
R2 in VGND 1e8
*E1 out20 0 out10 VGND {gain}
B1 out20 0 V=LIMIT(0,V(out10,VGND)*{gain},1)
AE1 out20 0 0 0 0 0 out 0 BUF ref={vt1} vhigh=1 tripdt={tripdt3}
.ends
*

* Standard output driver
.SUBCKT CD40_OUT_1X in out VDD VGND vdd3={vdd2} speed3={speed2} tripdt3={tripdt2}
.param trise1=80e-9*5.0/{vdd3}*{speed3}
.param Rout=500*5.0/{vdd3}*{speed3}
*
AE1 in 0 0 0 0 0 out10 0 BUF tripdt={tripdt3} trise={trise1}
*
E1 out20 VGND out10 0 {vdd3}
Rout out20 out {Rout}
*D1 0 out DIO2
*D2 out VDD DIO2
.ends
*

* 2-input NOR gate
* tpd 125n
* tr 100n
.SUBCKT CD4001B A B Y VDD VGND vdd1={vdd} speed1={speed} tripdt1={tripdt}
.param td1=1e-9*(125-40-10)*5/{vdd1}*{speed1}
*
XIN1 A Ai VDD VGND CD40_IN_1 vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
XIN2 B Bi VDD VGND CD40_IN_1 vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
*
A1 Ai Bi 0 0 0 Yi 0 0 OR tripdt={tripdt1} td={td1}
*
XOUT Yi Y VDD VGND CD40_OUT_1X vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
.ends
*
* 2-input exclusive OR-gate
* tpd 140n
* tr 100n
.SUBCKT CD4070B A B Y VDD VGND vdd1={vdd} speed1={speed} tripdt1={tripdt}
.param td1=1e-9*(140-40-10)*5/{vdd1}*{speed1}
*
XIN1 A Ai VDD VGND CD40_IN_1 vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
XIN2 B Bi VDD VGND CD40_IN_1 vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
*
A1 Ai Bi 0 0 0 0 Yp 0 XOR tripdt={tripdt1} td={td1}
*
XOUT Yp Y VDD VGND CD40_OUT_1X vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
.ends
*

*=====================

- - - Updated - - -

The text below should be named as:
LM339.asy

*=====================

Version 4
SymbolType CELL
LINE Normal -32 -32 32 0
LINE Normal -32 32 32 0
LINE Normal -32 -32 -32 32
LINE Normal -28 -16 -20 -16
LINE Normal -28 16 -20 16
LINE Normal -24 20 -24 12
LINE Normal 0 -32 0 -16
LINE Normal 0 32 0 16
LINE Normal 4 -20 12 -20
LINE Normal 8 -24 8 -16
LINE Normal 4 20 12 20
WINDOW 0 16 -32 Left 0
WINDOW 3 16 32 Left 0
SYMATTR Value LM339
SYMATTR Prefix X
SYMATTR SpiceModel LM339.sub
SYMATTR Value2 LM339
SYMATTR Description Quad Single Supply 3V/5V Comparator LM339
PIN -32 16 NONE 0
PINATTR PinName In+
PINATTR SpiceOrder 1
PIN -32 -16 NONE 0
PINATTR PinName In-
PINATTR SpiceOrder 2
PIN 0 -32 NONE 0
PINATTR PinName V+
PINATTR SpiceOrder 3
PIN 0 32 NONE 0
PINATTR PinName V-
PINATTR SpiceOrder 4
PIN 32 0 NONE 0
PINATTR PinName OUT
PINATTR SpiceOrder 5

*=====================

- - - Updated - - -

The text below should be named as:
LM339.sub

*=====================

* LM339 VOLTAGE COMPARATOR "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS VERSION 4.03 ON 03/07/90 AT 14:17
* REV (N/A)
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OPEN COLLECTOR OUTPUT
* | | | | |
.SUBCKT LM339 1 2 3 4 5
*
F1 9 3 V1 1
IEE 3 7 DC 100.0E-6
VI1 21 1 DC .75
VI2 22 2 DC .75
Q1 9 21 7 QIN
Q2 8 22 7 QIN
Q3 9 8 4 QMO
Q4 8 8 4 QMI
.MODEL QIN PNP(IS=800.0E-18 BF=2.000E3)
.MODEL QMI NPN(IS=800.0E-18 BF=1002)
.MODEL QMO NPN(IS=800.0E-18 BF=1000 CJC=1E-15 TR=807.4E-9)
E1 10 4 9 4 1
V1 10 11 DC 0
Q5 5 11 4 QOC
.MODEL QOC NPN(IS=800.0E-18 BF=20.29E3 CJC=1E-15 TF=942.6E-12 TR=543.8E-9)
DP 4 3 DX
RP 3 4 46.3E3
.MODEL DX D(IS=800.0E-18)
*
.ENDS

* Model for packaged LM339 devices
* 14-pin DIP, 4 comparators per package
* CONNECTIONS: Output 2
* | Output 1
* | | Positive Power Supply
* | | | Input 1 Inverting
* | | | | Input 1 Non-Inverting
* | | | | | Input 2 Inverting
* | | | | | | Input 2 Non-Inverting
* | | | | | | | Input 3 Inverting
* | | | | | | | | Input 3 Non-inverting
* | | | | | | | | | Input 4 Inverting
* | | | | | | | | | | Input 4 Non-inverting
* | | | | | | | | | | | Negative Power Supply (or Gnd)
* | | | | | | | | | | | | Output 4
* | | | | | | | | | | | | | Output 3
* | | | | | | | | | | | | | |
.SUBCKT LM339_DIP14 1 2 3 4 5 6 7 8 9 10 11 12 13 14
X1 5 4 3 12 2 LM339
X2 7 6 3 12 1 LM339
X3 9 8 3 12 14 LM339
X4 11 10 3 12 13 LM339
.ENDS

*=====================

 

[ADGAN]

Sorry for the late reply, was busy with project work & lectures. Thank you

 

[KerimF]

I bet you are much busier than I. Please take your time. Me too, I may be busy anytime unexpectedly.
Since I solved the attachment issue (see thread), I attached the previous files (as zip) after making some cleaning.