Optimizing case statement with large input

[stanford]

case (input[9:0])
  0: ...
  1: ...
  2: ...
  ...
  1023: ..
  default: ...
endcase

Let's say that there is a 10 bit input and have 1024 possible case statements. If I were to write the case statements in such a way, input == 0 will have the highest priority, and so on.

1. If this the timing is critical for this and priority is not important, would using "unique case" tell the tool that priority is not required so that it can optimize the path further?
2. How does the hardware look like if there is no priority and have many possible drivers?

Thanks!!

 

[KlausST]

Hi,

I assume you are talking about HDL.

Then you need to see that all the cases are processed at the same time = in parallel (in opposite to microcontroller code)
And you need to understand that only one "case" can be true.

Thus I see no "priority" at all.

Klaus

 

[stanford]

Hi,

I assume you are talking about HDL.

Then you need to see that all the cases are processed at the same time = in parallel (in opposite to microcontroller code)
And you need to understand that only one "case" can be true.

Thus I see no "priority" at all.

Klaus

Even then, if the cases are processed in parallel, the output needs to be driven based on some 'priority' when implemented with a tree of muxes right, so wouldn't it imply that there is priority?

For casez, there could be multiple cases that evaluate to true, so by default priority is given from top to bottom.

 

[FvM]

I think you are confusing priority with logic gate order.

In a fully decoded case statement, each input bit matters and has no priority over others. According to the logic gate order, bits have however different propagation delay which may matter. Gate order will be respectively optimized in timing driven synthesis.

Of course, it mostly matters for optimization what's inside the case statement.

Presently I don't see where the thread is targeting to.

 

[stanford]

I think you are confusing priority with logic gate order.

In a fully decoded case statement, each input bit matters and has no priority over others. According to the logic gate order, bits have however different propagation delay which may matter. Gate order will be respectively optimized in timing driven synthesis.

Of course, it mostly matters for optimization what's inside the case statement.

Presently I don't see where the thread is targeting to.

Maybe i dont understand how case statements get synthesized.

How is this realized in hardware?

case (input[1:0])
  0: ...
  1: ...
  2: ...
  3: ...
  default: ...
endcase

How will these two look different in hardware?

if (input[1:0] == 0)
  ...
else if (input[1:0] == 1)
  ...
else if (input[1:0] == 2)
  ...
else if (input[1:0] == 3)
  ...
else
  ...
endcase

 

[KlausST]

Hi,

For casez, there could be multiple cases that evaluate to true, so by default priority is given from top to bottom

I don't understand with your example how multiple can be true the same time.
In my eyes it can be 1 or it can be 2 but it can't be 1 and 2 at the same time..
or any other numbers...

Klaus

 

[FvM]

Nothing has to be synthesized unless you fill up the case construct with actual statements.

Finally a logic expression for each output bit assigned in the case construct is established which will be optimized according to resource usage and timing requirements.

 

[vGoodtimes]

case statements in verilog are syntax sugar for the chained if-else statements. synthesis vendors either infer that one and only one case can be reached, or a pragma (fullcase/parallelcase) is used. SystemVerilog adds unique case to add simulation checks if multiple statements are reached.

when the synthesis tool can't assume multiple states can't be reached, it has to implement the logic like the chained if-else including any priority structure that this implies.

 

[asdf44]

Maybe i dont understand how case statements get synthesized.

How is this realized in hardware?

case (input[1:0])
  0: ...
  1: ...
  2: ...
  3: ...
  default: ...
endcase

How will these two look different in hardware?

if (input[1:0] == 0)
  ...
else if (input[1:0] == 1)
  ...
else if (input[1:0] == 2)
  ...
else if (input[1:0] == 3)
  ...
else
  ...
endcase

These two examples will produce identical hardware. By default consider it a mux but as FvM points out the synthesizer will optimize further based on what's in the case/if statements.