Optimization Question
The NAND gate has two sereis NMOS transistors and two parallel PMOS transistors. So you cannot always obtain fall time= rise time.
However, if for an inverter the (W/L) of the NMOS is (W/L)n and that for the PMOS is (W/L)p for Fall time = Rise Time. For the worst case design of the NAND gate, you should set the W/L ratio of the NMOS transistors to 2*(W/L)n (i.e. twice that of the inverter) and that of the PMOS to (W/L)p (i.e. equal to that of the inverter)