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VCS MX is for both verilog and VHDL.
plus VCS 7.0 is suppose to be way better. A lot of stuff that is in VCS was donated to accellera for creating the next HDL standard of Systemverilog.
I can not belive in the capability of the mixed sim tools of Synopsys, it's trash.
The bese mixed VHDL/Verilog sim tool is still modelsim, but for pure verilog, vcs or nc are the best choice.
I can not belive in the capability of the mixed sim tools of Synopsys, it's trash.
The bese mixed VHDL/Verilog sim tool is still modelsim, but for pure verilog, vcs or nc are the best choice.
I don't think so. I use VCS + NANOSIM to do mixed mode simulation under "big standard logic" + "middle scale customed logic" environment. It is really great.
The most important thing is: current VCS only support VCS(master) + Nanosim(slave) cosimulation environment. But in the future, they will support Nanosim(master) + VCS( slave ) case. Do you know what it mean? It means you can replace any subcircuit in a custom block you want to know into a verilog behavior module.
I mean pure RTL simulation, bu code written by Verilog and VHDL, for mixed Verilog/VHDL/SPICE sim, there are some other chioces such as ADMS and ADiT, i have no idea which one is better for mixed hdl/spice simulators.
I mean pure RTL simulation, bu code written by Verilog and VHDL, for mixed Verilog/VHDL/SPICE sim, there are some other chioces such as ADMS and ADiT, i have no idea which one is better for mixed hdl/spice simulators.
Yep, for pure RTL Verilog/VHDL simulation, I think VCS is trash too.
For AMDS-> only suitable for big logic and medium analog custom block.
For Adit -> under spice +rtl environment,
[Disadvantage]: compared with VCS+Nanosim, Speed poor. and for verilog syntax support is also poor too.
[Advantage]: CHEAP!!!
For VCS+Nanosim -> under spice+rtl environment
[Disadvantage]: EXPENSIVE
[Advantage]: VCS support NEARLY all verilog syntax, VCS+Nanosim's speed is pretty good, MUCH better than Adit.
For my previous application, I need to replace some circuits in design, VCS + Nanosim is my best choice for mixed(rtl+spice) signal simulation,
I ever tried Adit , but it cannot support some verilog syntax( actually, a lot of verilog syntax it cannot support, if you put some timing checking syntax in your library, you will know what I mean). The speed difference
between them, for example, my application simulation takes 1 day in Adit, 20 minutes in nanosim+vcs.
I hope someone can supply me tool information like rtl+spice
co-simulation because my current VCS+Nanosim is too expensive.....
I mean pure RTL simulation, bu code written by Verilog and VHDL, for mixed Verilog/VHDL/SPICE sim, there are some other chioces such as ADMS and ADiT, i have no idea which one is better for mixed hdl/spice simulators.
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