I have an NMOS cascode current mirror which provides a reference voltage for a folded
cascode amplifier. Right now this transistor is going into sub-threshold region (Vgs<Vt).
What impact will this have?
Natural VT mismatch is going to be insignificant compared
to operating two FETS, one in linear and one in saturation,
for Id matching. Lower Vgs gives you a lesser headroom
requirement for Vds induced mismatching to recede as a
problem.
For the current mirror,In sub-thresold region you are not able to provide high impedance for tail current requirement as currents flowing is in nano amps.
For the current mirror,In sub-thresold region you are not able to provide high impedance for tail current requirement as currents flowing is in nano amps.