OpenSPARC T1 Version 1.1 Released

[gliss]

Sun has released an update of their OpenSPARC, open source CPU.
**broken link removed**

New open source modules
Disk Read/Write updates in simulator
New FPGA project for implementing some modules in an FPGA

 

[matthew_wang]

Is this opensparc related to Opencores?

 

[the_penetrator]

no, friend, nothing to do with the opencores site.

it is an open core (in Verilog i think) of the Sun Sparc Niagara, distributed by Sun themselves.

the_penetrator©

 

[gliss]

Yes, it is Verilog. It also includes software for a simulation environment. You can load Solaris onto the emulator created by the simulator. It also includes scripts for DC and Synplify synthesis.

 

[the_penetrator]

wow, sounds like big monster

do you know if it can fit (T1 + peripherals) in any FPGA (Virtex-II Pro or Virtex-4, the biggest ones)?

 

[dainis]

wow, sounds like big monster

do you know if it can fit (T1 + peripherals) in any FPGA (Virtex-II Pro or Virtex-4, the biggest ones)?

**broken link removed**

Results of FPGA mapping:

Preliminary results of FPGA mapping to Xilinx XC4VLX200 and Altera EP2S180 parts are listed below. These results are from the Synplicity software. Once you do actual layout in Xilinx or Altera FPGA, you will get final post-layout results.

Xilinx XC4VLX200 SPARC FPU CCX
LUTs 134,973 13,863 25,090
Utilization 75% 7% 14%
Altera EP2S180 SPARC FPU CCX
Estimated ALMs 74,280 6,855 19,589
Utilization 103% 10% 27%

 

[gliss]

wow, it uses a lot of FPGA resources.