Open multi files in verilog testbench

[cnspy]

I have to open a lot of file as

file1.txt
file2.txt
....
file1024.txt

How to open these kind of file name with simple method in verilog?

Such as use loop for it?

thanks.

 

[FvM]

Hello,

could be possible using $sformat() system task and string manipulation. But I didn't try cause I use generally VHDL testbenches.

Regards,
Frank

 

[cnspy]

Fvm, thanks a lot. I have try it and it work well.