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opamp settling simulation problem

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Aijue

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hi guys,
when i take my opamp for settling simulation, i got a strange result.The pic is in the attachment. The question is why the settling curve have a turning to become a smaller settling.
Did you have met such problem? What a headache.

Thanks!
[/quote]
 

dick_freebird

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You are seeing either a gain or bias transition; for example
a cascoded output will have a pretty constant current
until the guard device runs out of headroom and then
the mirror current will roll off in the manner shown. This
means small signal modeling is not to be trusted even
at V=0 (transition is pretty ugly right there).
 

    Aijue

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Aijue

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thanks freebird, i got some insights. My opamp is folded cascoded.
Do you mean when input a large pulse voltage, my current source MOS device is driven into linear region?
Could you tell me how to set the tail current and the cascode current?

Best regards!
 

FvM

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It's normal, that large signal step response is different from small signal.

Apart from an apparent static error, the shown step response looks somewhat overcompensated and far
from usual high speed OP behaviour with package parasitic inductances and similar real world phenomenia.
 

    Aijue

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Aijue

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Input pulse rise time is 0.1ns. I want the settling time is less than 10ns.
How's the relationship between the settling time and the rise time?
 

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