The problem is, as Klaus has explained, power supply sequencing and ramp up.
The larger problem is whether the +15 and -15 supplies ramp up towards regulation at the exact same rate. It can be done, but you would have to carefully trim the compensation loop, filter caps, load currents, etc.
Also, the +5 volt supply should be sequenced earlier than the +/-15 supplies.
National Semi had an old app note dealing with precisely this issue.
Now, if you cannot guarantee an equal ramp up and/or proper sequencing, the second best option is to use a 10k resistor in series with the op output ant then a BAT54S to protect the FPGAs input.