OpAmp design - estimation of unity gain

[EmbdASIC]

OpAmp design

Hi everyone,

I am designing a low voltage opamp. The target specs only state the f3db, but not ft, of my opamp. I am in need of ft before i calculate my aspect ratio of input transistor. (hence i dont know gm1 either).

Now assuming a two pole transfer function, after f3db = 500Mhz, can i esitmate at 12db/octave rolloff to guess my correct unity gain frequency. So incase my DC gain was 60 db, my unity gain should be around 500 x 5 = 2500Mhz at around the 0db gain ?.

Could any of you verify the above method for estimation of my unity gain?

Regards
EA

 

[dick_freebird]

OpAmp design

With very high DC gain in one stage your first pole is probably
at low frequency, not 500MHz. This really derives from
architecture as much as device frequency attributes.
Particularly
if you have a high impedance gain node with low bias currents.

Open loop 3dB bandwidth of 500MHz is pretty damn sporty
for any high DC gain amplifier. What sort of AVOL spec are
you looking at? Or is this a 3dB @ A=xx closed loop kind of spec?

You might find Linear Tech, ADI, National LVCMOS op amp
datasheets instructive both for how specs relate (big picture)
and what is feasible.

I'm not used to seeing input devices matter much to bandwidth.
But my op amp designs are pretty unsophisticated as a rule.

 

[rfsystem]

Re: OpAmp design

The story of dimensioning the max bandwidth of an opamp is much easier if you start from the end.

The opamp could not have more bandwidth than the output stage. The Gm/Cload of the output stage define the parasitic pole which could not be compensated or avoided. If the phase of the ouput stage reach -30° the unity gain of the opamp and the feedback network should go below unity. If the feedback network is -20dB (gain=10) the GBW could be ten times the critical phase frequency. Bipolar output stages are better for instance because a high Gm could be achieved at lower currents. If you using MOS you could bias the output stage device near subthreshold but that decrease the Ft.

So the dimensioning procedure is:

1. What is the Cload
2. How much current I have to spend for max amplitude and best Gm/Cload

Any gain before the output stage could be easy achieved. You can cascade 4 or more stages for +100dB. You can use Gain="e" amplifiers for maximum bandwidth at given DC-gain.

All that does not extend this basic limitation. Anyway the loop gain has to fall below "one" at this critical output defined phase.

After years I wonder how complicated most opamp dimensioning are in education. For myself I start with h-parameters at education and have to learn at work my own methods to make quick (<2min) opamp dimensioning.

 

[LvW]

Re: OpAmp design

Hi everyone,
.........
.........
... can i esitmate at 12db/octave rolloff to guess my correct unity gain frequency. So incase my DC gain was 60 db, my unity gain should be around 500 x 5 = 2500Mhz at around the 0db gain ?.

Could any of you verify the above method for estimation of my unity gain?

12dB/octave means 2nd order roll-off and leads to instability.
More than that, calculation (multiplication by 5) is incorrect.
A realistic roll-off with -6dB/octave is identical to -20 dB/dec.
Thus, a dc gain of 60 dB leads to a unity gain frequency which is three decades above the 3dB corner. (In your case: 500 GHz !!!). Are you sure with 500 MHz ?

 

[EmbdASIC]

Re: OpAmp design

Thanks guys.

@LvW
I assumed that initially my opamp is unstable as i start approaching, hence the pole would be nearer, that why 12db/oct. othewise after compensation i would have counted 6db.

I realize that my 500Mhz is the close loop f3db, which is more or less GBW, due to which simplifies everything.

Anybody working on 65nm ST process, i need some process parameters for hand caculations, essentially UnCox for n and p devices.

Thanks to all.

 

[LvW]

Re: OpAmp design

I realize that my 500Mhz is the close loop f3db, which is more or less GBW, due to which simplifies everything.

But realize: closed loop f3db is app. identical to the GBW only for 100% feedback (unity gain amplifier), unless you design a current feedback amp.

 

[EmbdASIC]

Re: OpAmp design

yes, true. so for a capacitve divider (with equal caps) give a beta = 0.5.

Which means a 60dB gain would perhaps be limited to 30dB ?