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opamp design - bias current of 10uA Vsupply=3.3v.

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ramya19

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opamp design

I am trying to design an opamp. I have supplied a bias current of 10uA Vsupply=3.3v. 10uA is flowing through the diffpair branches (current mirror as well as input pair) The problem is the input pair transistors are in cutoff and all others are in saturation. Please suggest me what to do.
 

standup

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opamp design

please check your common input voltage
 

ken_cn

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opamp design

I tihink your input common voltage is too low(or high) to turn on the input pair.
 

pianomania

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As others opinion , you should check you commond input range ,
, as my experience ,
the maximum input range is Vdd-Vgs_in-Vds(tail current MOS)
and the minimun is Vss+Vgs+ Vds-Vgs_in , it might be close to Vss , if we use PMOS input . If we use NMOS input , the relationship will be exchanged.
Then by changing the W/L , you can make input operate under saturation.
 

ashik_na

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i think VDS drop across tail current tranistor is higher than the designed value.So that will increase the threshold of input pair transistor.so the input pair goes to cut off.
solution :

1. reduce the VDS drop.
2. adjust the common input voltage.
 

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