Op amp output oscillation problem

[houly]

Hello all,
I have a problem with a AD8512 op amp used in simple follower stage. the input signal is a DC voltage equal to 2.5V which is stable and proper.

A resistor was added on the output and the feedback for limiting current (protection against short circuit). There is no problem on inputs, only the output oscillate (1.8MHz), the device is supplied +/-13V and filtered with a 47nF capacitors for each supply lines. Do you have any idea ? thanks a lot for your help.

Best regards.

**broken link removed**

 

[dick_freebird]

You've added a pole, R1*C(IN-), and if the op amp was only
marginally unity-gain-stable originally, it may now be not.

You might try adding a small capacitance from output
to IN-, and see if you can get back to stable without losing
too much bandwidth / load-step response.

 

[houly]

thanks a lot for your reply.

I wonder why the configuration of a follower is the worst case ? how can I calculate the gain and phase margin for this stage ? and how the cap placed in the feedback can create the pole ?

regards.

 

[LvW]

I agree with dick_freebird, however, what is the purpose of the resistor?
Do you want to increase the total output resistance of the opamp?
Why and where do you expect a shortage?

 

[FvM]

I wonder why the configuration of a follower is the worst case ?

By adding the resistor, you don't have a simple voltage follower any more. You most likely had only an oscilloscope
probe as load (as the 1.8 MHz oscillation suggests). It becomes worse, if you connect a real load.

A usual circuit to isolate capacitive loads repectively provide current limit uses two resistors and the capacitor suggested by
dick_freebird. For moderate loads, it may be sufficient to bypass the series resistance with a small capacitor.

 

[houly]

I just read an interesting article provided by TI (here is the link : focus.ti.com/lit/an/sloa020a/sloa020a.pdf)

page 6 just after the equation 16, they mention that a comparisoon is made with the direct gain equation. I think that is the A term of the equation 12 (A/(1+A*Beta) page 5 but I don't understand when they said : "The direct gain garnered by the comparison method is a-ZG/(ZG+ZF)" ; when I made the comparison, if the A is the direct gain term, the comparison is direct and the A term is : -a*ZF/(ZG+ZF) ... ?

could you help me please ?

regards

Added after 23 minutes:

I agree with dick_freebird, however, what is the purpose of the resistor?
Do you want to increase the total output resistance of the opamp?
Why and where do you expect a shortage?

2k resistor permit to limit the current in case of a short circuit on the output...

Added after 3 minutes:

A usual circuit to isolate capacitive loads repectively provide current limit uses two resistors and the capacitor suggested by
dick_freebird.

OK, I see but could you explain me how can I calculate the cap value ? and how can I calculate the impact of the phase and gain margin of the stage ?

regards

 

[LvW]

but I don't understand when they said : "The direct gain garnered by the comparison method is a-ZG/(ZG+ZF)" ; when I made the comparison, if the A is the direct gain term, the comparison is direct and the A term is : -a*ZF/(ZG+ZF) ... ?

Yes, I agree with you. I also do not understand the used term "direct gain" in connection with the mentioned expression. However, I suggest not to spend more time to this part of the document.
Without any doubt, the expression -a*ZG/(ZG+ZF) is the loop gain.
(By the way, the minus sign was forgotten in the formula given with Fig.5)

Concerning output protection, I think 200 ohms (instead of 2k) would suffice as the maximum possible output current is app. 50mA.

 

[FvM]

I guess, you are adding current limit, because you want to connect a load. Unfortunately, Cf can't be "calculated" without
knowing the maximum load capacitance. For this reason, I would prefer a circuit that isolates the load capacitance.

 

[houly]

Thanks a lot... you're right for the resistor value, i should puyt a lower one

I would want to know what is the method to calculate the phase/gain margin of this stage, and could you please help me to understand how can I calculate the value of the cap added for stability ?

regards

Added after 3 minutes:

Cf can't be "calculated" without
knowing the maximum load capacitance

the capacitance of the load doesn't exceed 1nF.

 

[LvW]

..............
I would want to know what is the method to calculate the phase/gain margin of this stage, ...........

1.) For "calculation", you need the actual gain/phase response of the opamp.
2.) A measurement is relatively complicated (open loop)
3.) Simulation gives a good picture of the margins available. There is a lot of information available in this forum how to simulate loop gain and the corresponding margins.
4.) However, the data sheet gives some rough information (Fig. 17). For unity gain application (with load cap 20 pF) the phase margin is app. 50 deg.

Added after 18 minutes:

Concerning load capacity, here is a good link for an introductory article:
https://www.analog.com/library/analogdialogue/archives/31-2/appleng.html

 

[FvM]

the load doesn't exceed 1nF

doesn't exceed? You would need several 100 pF Cf in your circuit to compensate it.

Actually, In-loop compensation according to the said Analog AN (the above mentioned two resistors and a capacitor scheme)
is the only suitable way, if the DC error with Out-of loop can't be accepted.

 

[houly]

Yes 1nF...

I try to calculate the incidence of the cap with the method presented in the application note mentioned above.

Cut the feedback on the minus input of the op amp and consider Vtest and Vreturn
to deduce the open loop gain which seem to be the best way to know the stability of a op amp stage.

Vreturn/Vtest=A×β

A is the "direct gain".
β is the gain of the feedback.

In my "new" circuit with compensation cap, I don't see how I can determinate the transfer function because there is no pull down in feedback, so how can I express the incidence of the cap and two resistors ?

thanks a lot for your help

here is the schematic...
**broken link removed**

 

[FvM]

- You have at least a 12 pF differential OP input capacitance as "pull down" in feedback.
- What's the purpose of R1 in the new circuit? OP internal output impedance?

 

[houly]

A usual circuit to isolate capacitive loads repectively provide current limit uses two resistors and the capacitor suggested by dick_freebird.

You suggest to add another one for isolating or I'm wrong ? I probably don't understand you...

 

[FvM]

As I clearly said, I wanted to suggest the same circuit that's named In-loop compensation in the ADI application note, LvW brought in.

 

[houly]

do you mean this (figure 3) ?


https://www.analog.com/library/analogdialogue/archives/38-06/capacitive_loading.html

 

[FvM]

Yes.