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Op-amp in pipeline ADC

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Chinmaye

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I have designed a 12 bit pipeline ADC. When I replaced the Op-amp in the 3 MSB pipeline stage with a new one, the behavior of 2nd, 3rd stages are weird. I am using the same op-amp in 1st, 2nd and 3rd stages. The first stage is working fine. The second stage and third stage are not behaving as expected at some voltages. Attaching the waveforms for reference. I am trying to understand why the op-amp is working fine in the first stage and not in the second and third stages. Any leads?
 

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  • Flip_around_output.pdf
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A blind guess would be that something is either
forced into clipping or overrunning the range of
scaled-higher-bit subtraction network. Should
be easy enough to "camp out where the trouble
starts" and start probing in detail, against a
snapshot of "where there ain't no trouble".

This where you earn your designer's paycheck.
 
Thank you for the response. I am attaching the screenshot of the circuit I am trying to simulate. In the attached screen shot, I am introducing a current source at Q to maintain the required common mode output level. While debugging the circuit, I found that, the output is getting corrupted for different inputs each time I try to simulate and hence I am unable to create a test case where the output is getting corrupted.

Also, I noticed that common mode output gain of the circuit is greater than 1 for some common mode inputs. Would this result is corrupted output?
Any suggestions?
 

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  • Two stage op-amp.JPG
    Two stage op-amp.JPG
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