To say so with some reason, you would have performed the AC analysis with a parametric sweep of output current set point. Did you?the phase magnitude plot doesn't seem to indicate a stability problem (see attached images).
Hi,
I agreee.
The feedback line from R4 back to U1_In- needs a series resistor.
The value is not critical. Try 1k.
Add a capacitive feedback from U1_out to U1_In-.
Try 1nF.
If the oscillation still exists, then try to increase R.
Klaus
I doubt that.The 1k resistor probably introduced too much of a voltage drop
That FET load is hugely capacitive and most op amps aren't real
happy about that kind of loading...
Hi,
- - - Updated - - -
Hi,
I doubt that.
The 10pA of input bias current multiplied with the 1k givens 10 nV. Is 10nV too much voltage drop?
***
You either use resistor OR capacitor. It is not an alternative solution. You need both in one circuit.
Klaus
Then this is not current into the OPAMP but through D4.The simulation shows the current in the 1k resistor to be about 2mA (see attached).
You have a single supplied OPAMP. I strongly recommend NOT to apply negative voltage.D3 conducts when a negative voltage is applied
Sure you mean a capacitor? In your latest schematic shows afeedback resistor.good results with only a capacitor between the output and the inverting input
Without a series resistor the impedance of the IN- node is very low ohmic. It is dominated by R4 = 0.5 Ohms.I found a similar single capacitor configuration in ramp
Then there should be a signal input resistor (to IN-) .... and then you have a nice integrator...forming a nice triangle output from a square wave input.but it is the only element between the op amp output and inverting input
Hi,
You have a single supplied OPAMP. I strongly recommend NOT to apply negative voltage.
Sure you mean a capacitor? In your latest schematic shows afeedback resistor.
Without a series resistor the impedance of the IN- node is very low ohmic. It is dominated by R4 = 0.5 Ohms.
So your feedback capacitor (1uF of post4) is more "capacitive load" than a true feedback. For sure this "may" prevent form oscillations. But it is dangerous, because the input and output stages tend to saturate with that high capacitve load. This may lead to new oscillations with changed frequency.
(BTW: the 1uF with the 0.5Ohms form a filter with cutoff frequency of 320kHz and an impedance of 0.7Ohms @ fc. But the OPAMP output is unable to drive a 0.7 Ohms load.)
Then there should be a signal input resistor (to IN-) .... and then you have a nice integrator...forming a nice triangle output from a square wave input.
(Maybe you could show us a picture of the circuit you are talking about)
Klaus
Perhaps you should give up the idea to implement the ramp generator and current source in a single OP stage.
I would recommend using (3) op amps, either in the usual integrator with buffer configuration, or using the circuit from your linked article (the (2) OpAmp configuration will give you better convergence closer to the final voltage level on the input waveform) and use an op amp with suitable slew rate and current output capability in a voltage follower configuration to drive the MOSFET/relay driver. Make sure that the Gain Bandwidth of the op amp which is amplifying the feedback signal difference from the input is much larger than that of the integrator configured op amp in the circuit above for stability. The large load capacitance and other factors that vary with the MOSFET switching on and off can too easily impact the feedback signal on your integrator op amp, and for the reasons above, it is trying to compromise too many different things to maintain stability over a usefully broad frequency range (IMO).
If this were to go into a $10 toy that was to be reproduced 10million times, I'd try harder to get it to work with 1 op amp, but if you want a well behaved, good control circuit for accurate experimentation, I'd spend the extra $2 in parts.
I believe the thread is rather instructive in an unintended regard:
How much time can be wasted in pursuing a bad design idea (the single OP linear ramp generator + current source).
It's surely not completely impossible to implement it, but it's against the principle of OP circuit design which tries to realize an almost ideal circuit function with a few passive components, possibly active components like diodes or transistors and as many OPs as required. I notice that the present diode circuit already involves a compromise solution for the ramp generator with an unwanted initial step.
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