How to design an op-amp with unity-gain bandwidth of 5MHz and maintain 50-60dB voltage gain? who could tell me which topology suitable for this?
Thanks
for the mentioned specs even conventional two stage opamp is suitable.
Which technology u r using?.
Well the design procedure is not fixed is changes according to what u want.
This is based on 0.35um 5V CMOS process.
I want output res to be low so using a series-shunt feedback.
Maybe enlarging my bandwidth-product can be a way, but how to do that?
First of all, I need to choose a appropriate structure.
Can you help me?
You go ahead with 2 stage op-amp. With 0.35u technology you can easily get gain of around 60dB. Avoid using the large diff pair as larger W may prove as diminishing return due to parasitic cap.
You can use nmos differential input pair with 2nd stage being inverter with active load. Increase the current of first stage to increase ur bandwidth. U can use differential pmos and nmos cascode structures to increase the resistance of first stage and hence gain. U can get a worst case gain of 80dB easily with this for power supply of 3.3V or above. Hope the input is not rail to rail.
Please take a look at this pic.
Actually, my input ranges from 80mV to 1.2V, and need output pass PMOS(MP8) could source 50mA current to drive a transformer. Power supply is 5V. Output swing should be 300mV to 4V
As simulation showed, the BW is very small, -3dB freq is around 1Hz.How to improve this?
Can you help ?
Thanks
How to design an op-amp with unity-gain bandwidth of 5MHz and maintain 50-60dB voltage gain? who could tell me which topology suitable for this?
Thanks
How to design an op-amp with unity-gain bandwidth of 5MHz and maintain 50-60dB voltage gain? who could tell me which topology suitable for this?
Thanks