One Simple Verilog Design Question

[javatea]

Hi Folks,
I will like to design a counter (from 0~4)
and only for odd state (counter=1,3), output = 1. otherwise =0
This module gets two input clk and rst

I wrote two different code for it.
Which one is better? Thank you so much


counter 01234 01234
output 01010 01010

////////////////////////////////////////////////////
// Code Style 1
////////////////////////////////////////////////////

module counter(input rst, clk, output reg out);

reg [2:0] tmp; // fixed

always@(posedge clk) begin
if (!rst) begin
out<=0;
tmp<=0;
end
else if (tmp==2'd4) begin
tmp<=0;
out<=0;
end
else if (tmp==2'd1 || tmp==2'd3) begin
tmp<=tmp+1;
out<=1;
end
else begin
tmp<=tmp+1'b1;
out<=0;
end
endmodule


////////////////////////////
// Code Style two
////////////////////////////

module counter(input rst, clk, output reg out);

reg [2:0]tmp; // fixed

always@(posedge clk) begin
if (!rst) begin
tmp<=0;
end
else if(tmp==4)
tmp<=0;
else
tmp<=tmp+1;
end

always@(tmp)
if (tmp==1 || tmp==3)
out=1;
else
out=0;
end

endmodule

 

[FvM]

Both suffer from the fact, that tmp can't never reach a value of four. tmp needs three bits. Apart from this problem,
with code style 2, the output can have glitches. This may be a problem depending on the usage of signal "out".

 

[javatea]

Oh yeah ~ for tmp variable, it need 3 bits, => [2:0] tmp
Beside this, Is there any bug ?
I remember we should better separate combinational and sequential part in our design. It could save more gate counts for us?
So, in practice, style 2 is better them style 1? correct?
Thank you