one random question regarding packaging of IC.

[Rahul Sharma]

Is it possible to package various IC, which are fabricated on different nodes (for example ADC on 130nm, processing unit on 28nm and trans-receiver on 65nm) on a single package chip.

To make my question more clear suppose i have 1.3mm*1.3mm die area and i made a processor on it and after packaging i got one chip of 3cm*3cm area. Now i have such 3 different ICs/dies and i want to package these three together on a single chip of 5cm*5cm area in which these three are connected together with bond wires as per the demand of SoC.

Can we do like this?

 

[ThisIsNotSam]

you can do something chip to chip bonding. each chip is still packaged on its own though.

 

[dick_freebird]

I think you will have some problems such as the need for a
finite distance between dice for the die attach process to
work properly, some extremely long and potentially crossed
bond wires (which for prototyping might be done by careful
bond figure art, specific loop height and pad-to-post map,
but would be a "hell no!" for anything production). In a real
production scenario you would lay out the chips with the
package already in mind, or perhaps engineer a multilayer
package for bumped dice that does a lot of the close-in
routing, maybe even better-engineered transmission line
characteristics for your transceiver and so on.

Assembly houses tend to barely tolerate multiple chips
per cavity and that's when you aren't bringing them a
doomed plan.

 

[Rahul Sharma]

I think you will have some problems such as the need for a
finite distance between dice for the die attach process to
work properly, some extremely long and potentially crossed
bond wires (which for prototyping might be done by careful
bond figure art, specific loop height and pad-to-post map,
but would be a "hell no!" for anything production). In a real
production scenario you would lay out the chips with the
package already in mind, or perhaps engineer a multilayer
package for bumped dice that does a lot of the close-in
routing, maybe even better-engineered transmission line
characteristics for your transceiver and so on.

Assembly houses tend to barely tolerate multiple chips
per cavity and that's when you aren't bringing them a
doomed plan.

Thanks for the answer . May i get more clarity on this !