tony_taoyh
Full Member level 2
One chip has three segments:
1) I/O pad ring (including one supply pin = VEXT, let's say 3V)
2) Core circuit (in VDD domain, let's say 1.8V)
3) One internal regulator (which generates VDD from VEXT).
If putting two guardrings between the "I/O pad ring" and the "Core circuit", in order to further enhance the latchup immunity:
1) P+ guardring: will be connected to VSS
2) N+ guardring in NWell: shall I connect it to VEXT or VDD? (a brief explanations for reason is highly appreciated).
Thanks a lot.
1) I/O pad ring (including one supply pin = VEXT, let's say 3V)
2) Core circuit (in VDD domain, let's say 1.8V)
3) One internal regulator (which generates VDD from VEXT).
If putting two guardrings between the "I/O pad ring" and the "Core circuit", in order to further enhance the latchup immunity:
1) P+ guardring: will be connected to VSS
2) N+ guardring in NWell: shall I connect it to VEXT or VDD? (a brief explanations for reason is highly appreciated).
Thanks a lot.