One question about system verilog `__LINE__ define

[xiaojigao]

There is a compiler derective in system verilog -- `__LINE__, it will expands to the current input line number. But I find it will return current line number -1.

For example, in below code(the left is line number):

1 initial begin
2 signal_a = 0;
3 signal_b = 1;
4 $display("current line is: %0d",`__LINE__);
5 end

When I run this code using ncsim, it will output:

current line is: 3

It's so strange, I think it should output "current line is: 4", because obviously this line number is 4, but not 3.

Can somebody tell me why?
Thanks a lot!

 

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[dave_59]

This could be interpreted as a tool bug. Since your example is not complete, how was it compiled?

 

[xiaojigao]

For example, I compile below file using Cadence irun:
1 module top;
2 initial begin
3 $display(" current line: %0d",`__LINE__);
4 $finish;
5 end
6 endmodule

This file is top.sv, I compile it using below simple way:
irun top.sv

Then it outputs result:
current line: 2

My irun version is 12.20-s014.