One clock cycle delay in pipelining adders

[shankar]

in designing pipelining adders i face difficultly in operating circuit with respect to clock. when i insert register for input and output pins.there is delay of one clock cycle which leads to malfunction.

 

[power-twq]

Re: pipelining adders

The pipeline technology will increase delay of the result.

it can increase throughput.

best regards

in designing pipelining adders i face difficultly in operating circuit with respect to clock. when i insert register for input and output pins.there is delay of one clock cycle which leads to malfunction.

 

[Sparc]

Re: pipelining adders

Inserting registers in any ckt will result in increased clock cycle Latency, by the no. of registers in the critical path. But as is said it will increase the throughput. So, when you insert I/O registers, it helps you in decreasing Input and Output delay, but as well cost you in terms of Clock cycles.

 

[Renjith]

pipelining adders

Shankar,
Things r not pretty clear with the way u mentioned ur problem. if you just put an I/O registers, there can't b any changes in the combo logic.
can u put the code here so that, all can have a look at it and give a soln for ur problem.

Best Regards,
Renjith