Oct 12, 2018 #1 R riz1679 Newbie level 3 Joined Oct 5, 2018 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 49 Hi all, I am new to digital design. shown in the figure there is an 'addr' signal which is generated by some state machine. I want to sample the input data 'data_rec_in' with one clock cycle delay. Below is the code for the block. Code: [ATTACH=CONFIG]149499._xfImport[/ATTACH]
Hi all, I am new to digital design. shown in the figure there is an 'addr' signal which is generated by some state machine. I want to sample the input data 'data_rec_in' with one clock cycle delay. Below is the code for the block. Code: [ATTACH=CONFIG]149499._xfImport[/ATTACH]
Oct 12, 2018 #2 KlausST Advanced Member level 7 Joined Apr 17, 2014 Messages 25,155 Helped 4,868 Reputation 9,757 Reaction score 5,535 Trophy points 1,393 Activity points 168,327 Hi, usually just a (additional) DFF is used to delay by one clock cycle. Klaus