signal load0 : std_logic_vector(7 downto 0) :=(others => '0');
signal load_reg : std_logic_vector(3 downto 0) := x"4";
.
.
begin
process(mclk, all_rst)
begin
if all_rst='1' then
load0 <= x"ff";
elsif rising_edge(mclk) then
case load_reg is
when x"0" => load0 <= x"00";
when x"1" => load0 <= "00000001";
when x"2" => load0 <= "00000010";
when x"3" => load0 <= "00000100";
when x"4" => load0 <= "00001000";
etc....
when x"7" => load0 <= "10000000";
when others => load0 <= x"ff"; -- reset value
end case;
end if;
end process;
load_out_o <= load0;