On live data processing with Altera FPGA Cyclone IV

[flote21]

Hello everybody,

I am inside of a project where I am in charge of the VHDL design using an ALTERA FPGA Cyclone IV. This FPGA has to control a RGB sensor and this RGB sensor provide the information of the pixel output through a LVDS interface. In my FPGA design I implemented a module in order to control the RGB sensor and receive the pixel output.

The value of 4 pixels are reveived in parallel with a frequency of 150MHZ. Si I had to designe a module for interfacing the FPGA with the sensor. This module was implemented in a succesfully way because I am able to see the values of the pixels on real time thanks to the Signal TAP (it is like chipscope in xilinx). But in this point I need to do some kind of data processing on real time before send this data to the PC via Ethernet.

The data processing that I need to do consisits in adding up the RGB infomation. I mean, every 150MHZ I receive 4 pixels in parallel. Thanks to the known Bayer Pattern, it is possible to predict which pixels have information of Red, Green or Blue. Then I need to make small packages of 32 pixels and adding up the values of the pixels with the same color and send the total value to the PC.

And it is in this point where I don¨t know exactly how to do programm in VHDL. I have nerver handle d on real time data with a FPGA and I have never made a data processing on real time, too. For this reason I would like to ask in this forum if someone could give me some tips or some good documentation to read to reach my target.

Thank you very much in advance.

 

[shaiko]

I don't mean to heart your moral - but if you don't know any VHDL you have A LOT of learning ahead.

As a starting step:

1. Make sure you're VERY familiar with how digital logic works (MUX, Flip Flop, Gates, etc...).
2. Learn the basic syntax rules of VHDL (what is an entity, architecture, signal, etc...).
3. Practice writing the simple digital logic from #1 with the knowledge you gained from #2.
4, During #3 Post very specific questions on this forum.

Good Luck!

 

[flote21]

Hi Shaiko, thank you very much for you answer.

I know VHDL. In fact i have designed the FSM to generate the control signals of the sensor. But I have never handled data on real time in a FPGA. I figure out that I will need some kind of FIFO o RAM memory to store tha data received and make a post processing of the information later. Is this truth? Or Can I make a data processing directly without using any internal RAM memory??

Thanks.

I don't mean to heart your moral - but if you don't know any VHDL you have A LOT of learning ahead.

As a starting step:

1. Make sure you're VERY familiar with how digital logic works (MUX, Flip Flop, Gates, etc...).
2. Learn the basic syntax rules of VHDL (what is an entity, architecture, signal, etc...).
3. Practice writing the simple digital logic from #1 with the knowledge you gained from #2.
4, During #3 Post very specific questions on this forum.

Good Luck!

 

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Hi Shaiko, thank you very much for you answer.

I know VHDL. In fact i have designed the FSM to generate the control signals of the sensor. But I have never handled data on real time in a FPGA. I figure out that I will need some kind of FIFO o RAM memory to store tha data received and make a post processing of the information later. Is this truth? Or Can I make a data processing directly without using any internal RAM memory??

Thanks.

How much buffering you have depends a lot on what your architecture looks like.

1) Any clock domain transfers will require a FIFO/buffer.
2) Any place the data changes from streaming to bursting or from bursting to streaming will require a FIFO/buffer
3) Any time you need to store data for a period of time before it's used (delay) will require FIFO/buffer

Given this you will require at a minimum a buffer at the output that feeds the Ethernet controller as it will be on a different clock domain and will burst data.

For the processing you will want to pipeline the design so the processing can be done in stages. This could be done at the input clock rate, which means you won't require any buffering until something changes that requires you to use a different clock domain or change the streaming of the data.

The best advice I can give you will be to draw up a block diagram of the processing you require, the control, the memory (if required between blocks), and the external interface blocks before you write one line of VHDL. Without a design you will likely end up with a non-functional FPGA design that requires an excessive amount of debugging. Keep in mind VHDL is a hardware description language so you'll need to know what hardware you want to write the code.

Regards

 

[flote21]

Ok, I will follow your advise of drwaing a bock diagram with the data processing that I want to do. But i am a little bit afraid about the timming. If I have to make the "adding on real time, and I have to store the samples in a FIFO, in the mean time what i ma reading the FIFO and process the data read, I am missing incoming data. Maybe I will need to implement a ring memory, right?

Other question is, how can I measure the LVDS channels with a normal Oscilloscope? Is it possible with the normal probes? Or I need special ones?

thanks.

How much buffering you have depends a lot on what your architecture looks like.

1) Any clock domain transfers will require a FIFO/buffer.
2) Any place the data changes from streaming to bursting or from bursting to streaming will require a FIFO/buffer
3) Any time you need to store data for a period of time before it's used (delay) will require FIFO/buffer

Given this you will require at a minimum a buffer at the output that feeds the Ethernet controller as it will be on a different clock domain and will burst data.

For the processing you will want to pipeline the design so the processing can be done in stages. This could be done at the input clock rate, which means you won't require any buffering until something changes that requires you to use a different clock domain or change the streaming of the data.

The best advice I can give you will be to draw up a block diagram of the processing you require, the control, the memory (if required between blocks), and the external interface blocks before you write one line of VHDL. Without a design you will likely end up with a non-functional FPGA design that requires an excessive amount of debugging. Keep in mind VHDL is a hardware description language so you'll need to know what hardware you want to write the code.

Regards

 

[TrickyDicky]

Fifos are dual ported, so you can write from port A and read from port B simultaneously.

 

[FvM]

Ok, I will follow your advise of drwaing a bock diagram with the data processing that I want to do. But i am a little bit afraid about the timming. If I have to make the "adding on real time, and I have to store the samples in a FIFO, in the mean time what i ma reading the FIFO and process the data read, I am missing incoming data. Maybe I will need to implement a ring memory, right?

I'm under the impression that you're primarly lacking a clear data processing algorithm. Once you have it, the design of the data path should be more or less obvious.

Other question is, how can I measure the LVDS channels with a normal Oscilloscope? Is it possible with the normal probes? Or I need special ones?

A regular passive probe is usually sufficient to see data bits and verify signal levels at lower data rates. If your budget allows, you should at least consider to buy a single ended active probe or possibly a resistive high speed probe. Differential active probes are available as well, but more expensive. Sufficient oscilloscope bandwidth >= 500 MHz is required (or more for highest LVDS data rates).

 

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But i am a little bit afraid about the timming. If I have to make the "adding on real time, and I have to store the samples in a FIFO, in the mean time what i ma reading the FIFO and process the data read, I am missing incoming data. Maybe I will need to implement a ring memory, right?

I think you're viewing this more like software execution, where everything has to happen sequentially (e.g. write FIFO, read FIFO, perform calculation, output calculated value,...write FIFO, read FIFO...)

In an FPGA (hardware design) you can be simultaneously writing to a FIFO, reading from a FIFO, perform calculations using a previous value read from the FIFO, outputting a previously finished calculation, all in parallel on the same clock cycle.

What I typically do to determine the timing is figure out the calculations I need to perform, then draw up a pipeline diagram that shows where each piece of the calculation resides in the pipeline (i.e. where each piece sits between flip-flops). From that diagram it's easy to write the RTL.

Regards