[SOLVED] On chip clocks for at speed testing in DFT

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c_ssood

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Please list all the major inputs to a on chip clock generator used for generating clocks for the at speed testing of DFT.
 

Please list all the major inputs to a on chip clock generator used for generating clocks for the at speed testing of DFT.

a base clock, for starters.
assuming this is PLL based, it has to be configured to get the right multipliers.
 

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