okay to omit via annular ring from inner layers?

[quantized]

Suppose I have a via in a four-layer board, and the via connects to traces only on the outer two layers. Is it okay to omit the annular ring from the inner two layers? Will this cause problems when plating the through-hole, or is the annular ring part of the plating process only on the outer layers? I'll admit I don't really understand the plating process, chemically, very well.

The goal here is to be able to get a trace between a pair of 1.0mm-pitch vias. Most low-end board houses require 0.2mm width/space on inner layers and 0.3mm smallest drill, so for two vias at 1.0mm pitch with annular rings you can't run a trace between them. No, I can't change the via pitch (dictated by a component footprint).

With no annular ring there's a 0.25mm space from either side of the trace to the drill. Fab claims drill registration is 0.09mm so that sounds like a very large margin of error. I just want to know if leaving out the inner-layer annular ring will cause the via plating to fail.

If it's okay to omit the inner layer annular rings, what about the outer layer rings for vias that run between two inner layers or one outer layer and one inner layer? Clearly that is a lot more risky, but is it okay? I'm guessing not but if I'm wrong that would be great!

Thanks!

 

[barry]

Interesting question. I think this is a question for the PCB manufacturer. My guess is that you need some minimum annular ring to insure the pth is solid, but not sure if it needs to be the same as on outer layers. I'm interested to know what you find out.

 

[quantized]

Interesting question. I think this is a question for the PCB manufacturer.

Well, I don't want to be tied to a single PCB manufacturer, so I'm looking for a general manufacturer-agnostic answer.

Sort of like how if you stick to 0.15mm trace/space and 0.3mm drills you can get your board made cheaply just about anywhere. There's a certain baseline spec that works everywhere and I'm trying to figure out if this is part of it.

I just sent a board with the above no-inner-annulars to a bunch of bargain-basement chinese PCB houses; I'll see if they come back okay.

 

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I just sent a board with the above no-inner-annulars to a bunch of bargain-basement chinese PCB houses; I'll see if they come back okay.

They will all probably come back and say everything is fine and they can build the boards, I'm sure they will want their money before they ship the boards...only after you receive them, and they don't work, will you find out their process doesn't work.

 

[FvM]

Generally, it's preferred to remove unconnected via pads on inner layers. But usual design rules require a larger drill to copper than copper to copper spacing. 0.25 mm drill to copper may be too small.

 

[barry]

They will all probably come back and say everything is fine and they can build the boards, I'm sure they will want their money before they ship the boards...only after you receive them, and they don't work, will you find out their process doesn't work.

I think you need to find yourself a more reputable board manufacturer.

 

[ads-ee]

But usual design rules require a larger drill to copper than copper to copper spacing. 0.25 mm drill to copper may be too small.

I think you need to find yourself a more reputable board manufacturer.

This is where the reputable board house will ask you...Are you smoking something funny? And then proceed to tell you why your design can't be built without changes.

I remember someone telling me they always send a new job to a new board house with some known problem that should be flagged as a manufacturing DRC problem, if the board house doesn't say anything they look for another board house.

 

[quantized]

They will all probably come back and say everything is fine and they can build the boards, I'm sure they will want their money before they ship the boards...only after you receive them, and they don't work, will you find out their process doesn't work.

Uh, yes... that was exactly my plan. You know, experimentation.

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I think you need to find yourself a more reputable board manufacturer.

Barry, please re-read the thread. I can't afford to be locked in to a specific board manufacturer, so asking any specific board manufacturer -- no matter how "reputable" -- if their specific fab can do this will not answer my question.

The question is if this structure is acceptable on the "least common denominator" PCB process, and if it is not, then what is the reason why it is not acceptable?

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Generally, it's preferred to remove unconnected via pads on inner layers. But usual design rules require a larger drill to copper than copper to copper spacing.

Thank you FvM, for being the only person in this thread who actually attempted to answer the question instead of sneering at my use of non-diamond-encrusted PCB houses.

0.25 mm drill to copper may be too small.

Really? Every board house I've seen calls for at most 0.10mm annular rings around vias and 0.15mm trace spacing. So if the drill registration can be off by 0.25mm or more it will cause outrageous problems for all sorts of other things too. Copper-to-drill of 0.25mm has to be mechanically adequate or else the rest of their design rules are wrong (which is always a possibility, but if that's the case there are much bigger problems).

I was mostly wondering if there is some chemical reason related to the plating process (which I don't understand as well as things like layer registration) that would require annular rings on the inner vias. If they aren't required for chemical plating reasons then I'm safe.

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I remember someone telling me they always send a new job to a new board house with some known problem that should be flagged as a manufacturing DRC problem, if the board house doesn't say anything they look for another board house.

If your engineers rely on the board house to catch their mistakes they ought to be fired.

 

[barry]

Barry, please re-read the thread. I can't afford to be locked in to a specific board manufacturer, so asking any specific board manufacturer -- no matter how "reputable" -- if their specific fab can do this will not answer my question.

The question is if this structure is acceptable on the "least common denominator" PCB process, and if it is not, then what is the reason why it is not acceptable?

[

First of all, I read your thread just fine.

I said nothing about being "locked in". The fact is, different manufacturers have different capabilities. If you want to be able to be "not locked in", then design for worst-case and keep your crappy attitude to yourself.

 

[quantized]

First of all, I read your thread just fine.

Evidently not because you have only just now figured out what I was asking.

If you want to be able to be "not locked in", then design for worst-case

This is exactly what I have been doing.

This thread asks the question: does the worst-case allow to omit annular rings from inner layers? And if it does not, what failure (specifically) could result from omitting these rings?

This thread does not ask people to preach to me about which PCB house I ought to be using. Yet somehow any thread that indicates even the tiniest bit of cost sensitivity brings you people swarming like flies. Begone!

 

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If your engineers rely on the board house to catch their mistakes they ought to be fired.

You should take your own advice to barry and reread my post.

They ADD a mistake they know should be a problem for the board house to manufacture. Specifically to check how honest and observant the board house is.

I've seen bad board houses promising supper cheap prices to sucker clueless manaagers into switching. Then the competent and very good engineers get stuck trying to fix RF boards that have horrid impedance control problems.

 

[quantized]

Specifically to check how honest and observant the board house is.

Yes, I know what you're talking about. And it's stupid.

If the PCB house is paying some highly-trained human to manually look at my boards, they're Doing It Wrong. There is no way they will be cost-competitive for my weekly 10-board prototype runs (which I do MONTHS of before placing the big production run). Any board house with this kind of cost structure is not going to be able to afford my business.

I tell you people, the PCB industry is stuck in the dark ages. The VLSI world long ago gave up on human design inspection. There's a machine-readable DRC deck that specifies, unambiguously, exactly what the fab can manufacture. If your GDS passes DRC, they're claiming they can make it. It's not up to a human.

I've seen this stuff happen with crap board houses promising supper cheap prices to sucker clueless manaagers into switching.

And they deserve what they get if they don't do a test run first.

Take your manufacturing snobbery somewhere else, it's getting increasingly dated.

 

[FvM]

Really? Every board house I've seen calls for at most 0.10mm annular rings around vias and 0.15mm trace spacing. So if the drill registration can be off by 0.25mm or more it will cause outrageous problems for all sorts of other things too. Copper-to-drill of 0.25mm has to be mechanically adequate or else the rest of their design rules are wrong (which is always a possibility, but if that's the case there are much bigger problems).

I was mostly wondering if there is some chemical reason related to the plating process (which I don't understand as well as things like layer registration) that would require annular rings on the inner vias. If they aren't required for chemical plating reasons then I'm safe.

There are two parameters demanding an additional margin for drill to copper spacing.

You already mentioned registration accuracy. The other problem is that voids in the substrate and prepreg layers can be filled with process chemicals or being metallized and create a short to nearby traces during throughplating. That's the reason why drill to copper and drill to drill spacing is usually larger than copper to copper. As an example, the drill to copper rule may be as large as 8.5 mil for 3 mil copper to copper. I believe that a safe rule for 0.15 mm (6 mil) copper to copper industry standard PCB technology could be 0.3 mm (12 mil) but surely no less than 0.25 mm. You should ask your PCB manufacturers for respective design rules.

 

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You should take your own advice to barry and reread my post.

They ADD a mistake they know should be a problem for the board house to manufacture. Specifically to check how honest and observant the board house is.

I've seen bad board houses promising supper cheap prices to sucker clueless manaagers into switching. Then the competent and very good engineers get stuck trying to fix RF boards that have horrid impedance control problems.

Yes, I know what you're talking about. And it's stupid.

If the PCB house is paying some highly-trained human to manually look at my boards, they're Doing It Wrong. There is no way they will be cost-competitive for my weekly 10-board prototype runs (which I do MONTHS of before placing the big production run). Any board house with this kind of cost structure is not going to be able to afford my business.

I tell you people, the PCB industry is stuck in the dark ages. The VLSI world long ago gave up on human design inspection. There's a machine-readable DRC deck that specifies, unambiguously, exactly what the fab can manufacture. If your GDS passes DRC, they're claiming they can make it. It's not up to a human.

And they deserve what they get if they don't do a test run first.

Take your manufacturing snobbery somewhere else, it's getting increasingly dated.

Wow, where did all this hostility come from? I'm quite upset with the attacks you are making on what I was just suggesting you watch out for by using the cheapest board house you can find.

Also where did I say anything about a HUMAN looking at the GDSII information. I was just mentioning I've worked at places that would send out boards for test runs with a new house and they board house would come back saying no problem, but the boards would come back with all kinds of issues, registration issues, etching issues, impedance problems, etc. Now I'm sure you think I'm talking about Chinese manufacturers (which is probably why you are getting so defensive and angry with barry and I). I'm talking about both Chinese and US board houses including one that was local. The group I was with only had like 3 house certified to build our boards due to so many problems with other houses.

But hey I'm sure you'll attack me again for saying anything that is against your opinions.

 

[quantized]

FvM, thank you again for your very helpful and instructive reply.

The other problem is that voids in the substrate and prepreg layers can be filled with process chemicals or being metallized and create a short to nearby traces during throughplating. That's the reason why drill to copper and drill to drill spacing is usually larger than copper to copper.

Ah, totally fascinating; I get it. The drill strikes a void in the FR-4, thereby exposing it to the outside air; once exposed it gets electroplated, creating a short if the drill was too close to any copper.

Yes, I can see why this calls for extra drill-to-copper spacing.

Fortunately this problem would manifest as reduced yield rather than a total failure of the entire prototype run (the voids are placed randomly, so this sort of defect can't kill every single board in a batch the way a minimum-spacing violation can). For this particular job we have all-pin-pairs boundary scan and we can afford to junk a few boards, so I'm comfortable with the risk in this particular case.

Thanks again for explaining the how and the why, so I can learn! -- instead of yelling at me to spend more money and stay stupid

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I was just suggesting you watch out for by using the cheapest board house you can find.

Yes, I know, but this thread is not about board house recommendations or budgeting. I really did not ask for advice on that and I feel like you hijacked the thread in a rather brazen way there.

This is a constant frustration for me when asking questions about PCBs. The answer to every question seems to be "if you even have to ask that question you aren't using a highly-enough pedigreed PCB house"... this makes even less sense when the question is about understanding broad industry norms to ensure design portability across fabs.

I don't know why the PCB world has this weird habit of shrieking "use a different manufacturer" as the answer to every question. But it is really super-irritating.

 

[senilicus]

Basically there are two situations,

- The PCB manufacturer will remove unused lands on inner layers, to avoid drifting of the unconnected pads during the pressing/heating cycle of the manufacturing process. This is business as
usual . No problems here.

- Remove them by design, sometimes called "skipped via's" in order to use the extra space. But there is one MAJOR drawback. As long as the via hole is drilled exactly in the middle of
the via pad, there is no problem. But we do not live in a perfect world and some misalignment will occur.
If the via hole is not in the middle of the via pad, but near the edge of the pad it will, most likely, cause trouble on the copper of the inner layers with the risk of being drilled through one of your traces
it may cause an open, and after plating it may cause a short between the trace on the inner layer and the via..


So in General (imho), BAD IDEA!