Offset of folding signals

[kickbeer]

Hello,

I'm having a problem to determine the accurate zero crossing of my folding signals. When i compare the ideal zero crossing with the simulate zero crossing there is a deviation aroun 3mV. I have tried to make the size of differential pair transistor larger but i still cannot get the value which is close to ideal. There is always an offset. Anyone have idea on how to solve this?

 

[dick_freebird]

There can never be a consistent, zero offset in a single
ended output system. Only balanced symmetry can eliminate
systematic errors that unbalance the balanced front end
pair's effective transfer function.

The more gain you have in differential circuitry before
you go single ended, the more you reduce the "input
referred single ended error" component of input offset.
But you pick up more stabilization woes with more stages.
Cascoding output / gain stages can drive up the gain and
remove other common-mode sensitivities in those stages,
perhaps helping further. To the extent that your first diff-
to-single conversion point is the culprit, upping gain there
helps you match load-mirror to gain stage current density
more ideally, making the Vds of the gain stage match
the Vds of the mirror is good, etc.

 

[kickbeer]

Hi dick_freebird,

For ur info my output of folding circuit is differential but input is single. I tried to make W and L as large as possible but then there is limit that my circuit doesn't function anymore. I have just followed the rule of 1÷(√WL). You can see my schematic on the attachment. It is folding amplifier with transimpedance amplifier. I'm not planning into cascading and there may be a problem with biasing??? Can you have a look at it? Thanx in advanced