odd number clock divider

[ASIC_intl]

Ho to design a odd number clock divider?

 

[windzjy]

Give u some materials,it will help you!

 

[A.Anand Srinivasan]

design a counter which resets after the particular odd number count... and design a logic which gives 1 only one of the states of the counter....

 

[avimit]

Very simply you can use a ring counter. That is a shift register, with N flipflops in it, and at reset the value of one of the register is 1, rest are 0. During the shift operation, the LSB should feed back to the MSB in case your shift direction is 'right' i.e divide by 2 OR if your shift direction is left, ie multiply by 2, MSB should feed back into LSB.
You can now take o/p form any FF, and the o/p freq will be Input Freq/N.
Hope it helps
Kr,
Avi

 

[Nir Dahan]

you can look at some divide-by-3 solutions here:

https://asicdigitaldesign.wordpress...cal-interview-question-the-standard-solution/

and here:

https://asicdigitaldesign.wordpress.com/2008/01/31/ultimate-technical-interview-question-take-2/

If you understand the principle of the solutions you can take it from there to any odd number divider. Notice that these solutions assume you want a 50-50 duty cycle on the output!

ND.

https://asicdigitaldesign.wordpress.com