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OCB2Avalon Bus Bridge Verification

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shanebond

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Hi, I am new to verification and I have been assigned a task to verify the OCB2Avalon bus bridge design
I planned to use system verilog and UVM to build my verification platform.
I need some idea on how to verify this design ?
OCB - On the Chip Bus - Local bus
This OCB is driven by MPC8377EEC Mircocontroller from freescale and which is the master.
The OCB will connect to the Altera Arria FPGA which has the Avalon bus technology primitive. The Avalon bus will connect to the varion block in the design which going to be the slave for Avalon. Avalon master resides in the bridge design. bridge will act as slave to OCB master.
In general I want to know what are the things to be considered from the bus bridge design to create the verification test cases, verification scenarios from the design point of view ?
Initially I need to create a verification plan based on this requirement.
 

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