nxm SHIFT REGISTER IMPLEMANTATION BY VHDL

[gnrbyrm]

Hello everybody , i am doing a shift register project that operates "n x m" bit . Here "m" is bitwith, "n" is number of "m's". I handled my projeck by sampling register using Flipflops and achieved it. Register section works well. Now i have to multiply register "n" times . here i have some difficulties and i have two subtle erros . What could be solution. thnks for replies

here they are:

1. Near Din_in_unit type conversion doesnt match type std_logic_vector
2. Actual of formal output DOUT_reg cannot be expression



here is the code

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity nxmBitShiftReg is
generic (n : integer:=4;
         m : integer:=8
);
    Port ( CLK : in STD_LOGIC;
           CE : in  STD_LOGIC;
           SR : in  STD_LOGIC;
              OPMODE : in STD_LOGIC_VECTOR (1 downto 0);
              SRINIT : out STD_LOGIC_VECTOR ( m*n-1 downto 0);
           DIN : in  STD_LOGIC_VECTOR (m-1 downto 0);
           DOUT_mreg : out  STD_LOGIC_VECTOR (m-1 downto 0); -- output of multiplied registers
              DOUT_f : out STD_LOGIC_VECTOR (m*n-1 downto 0)
              );
end nxmBitShiftReg;
 
architecture Behavioral of nxmBitShiftReg is
type DIN_in_unit is array  ( n-1 downto 0 ) of STD_LOGIC_VECTOR ( m-1 downto 0 )  ;
type DOUT_out_unit is array  ( n-1 downto 0 ) of STD_LOGIC_VECTOR ( m-1 downto 0 )  ;
signal i : integer;
 
component m_bit_register
Port (     CLK : in STD_LOGIC;
           SR : in  STD_LOGIC; 
           DIN_reg : in  STD_LOGIC_VECTOR (m-1 downto 0);
           DOUT_reg : out  STD_LOGIC_VECTOR (m-1 downto 0)            
              );
end component;
begin
multiple_registers : for i in 0 to n-1   generate   --register instantiation n times
    begin  --"begin" statement for "generate"
     Registr : m_bit_register
     PORT MAP ( CLK => CLK ,SR=>SR , DIN_reg=>DIN_in_unit(i), DOUT_reg =>DOUT_out_unit(i) );            
end generate multiple_registers;
end Behavioral;

---

 

[FvM]

1. Near Din_in_unit type conversion doesnt match type std_logic_vector
2. Actual of formal output DOUT_reg cannot be expression

What do you mean with type conversion? The actuals must be signals (and might use type conversion in addition). But there are no signals connected to the data ports in your instantiation, only types and a generate variable.

There are other points, like the unclear connection to design port signals. But you should start using correct signals in the instantiation.

 

[gnrbyrm]

i noticed it today. i didnt know before whether defining signals in logic vector arrays are necessary. I think now this part of code is solved . i have been created whole code now i have one error still . "expecting type void for <Behavioral>/ Do you have any idea what can cause this error? `

 

[FvM]

Do you have any idea what can cause this error?

Not particularly. Maybe a Xilinx specific issue. One point is that the generate construct don't use a begin statement unless it's generating signals or constants. May be it confuses the design compiler. In case of doubt I have to look at the exact final code.