NWELL under bump pad layout??? help!!

[EEsj]

Hi I am trying to layout a bump pad. my layers (assume following DR) look like this

bump pad marking layer
top_metal layer
nwell (floating)

this does not give me any DRC errors which is what i expect.

When i incorporte this bump pad in my overall layout I recieve an nwell stamp error.

The DRM i am using calls for NWELL to be placed underneath wire bond pands so i assumed that this is the same for bump pads. please correct me if i am wrong

 

[dick_freebird]

I don't know what a "stamp rule" is, but expect the purpose of
NWell is to provide an isolation against the pad capacitance
which might push undesired AC currents into the substrate.
The NWell would be tied to wherever you think is the best
current return, to minimize circuit perturbations. Floating
only reduces capacitance by series, and would not assert any
particular destination for the currents.

 

[erikl]

nwell (floating)
...
this does not give me any DRC errors which is what i expect.
...
When i incorporte this bump pad in my overall layout I recieve an nwell stamp error.

"nwell stamp error" means it is floating, as you stated. Just connect it to an appropriate voltage level, as dick_freebird adviced, in doubt to VDD.