anonymous.
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how does Nvidia build their cache memories ??
In page 8 of this document you can see that each SMX has 32 Load/Store units. at least 16 of them are operating at a time.
how do they build a cache memory to accept 16 addresses. is it possible to build a 16 port cache memory ? do they use a single very wide port ?
what techniques are used for something like this ??
In page 8 of this document you can see that each SMX has 32 Load/Store units. at least 16 of them are operating at a time.
HTML:
http://www.nvidia.com/content/PDF/kepler/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdfhow do they build a cache memory to accept 16 addresses. is it possible to build a 16 port cache memory ? do they use a single very wide port ?
what techniques are used for something like this ??
