nrzi encoder decoder

[franticEB]

Hi i've to design a NRZI encoder / decoder system in VHDL.
The encoder and decoder will be implemented on 2 different fpgas (tx,rx)
I've wrote this for encoder

entity NRZI_ENCODER is
    Port ( CLK : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end NRZI_ENCODER;

architecture Behavioral of NRZI_ENCODER is
signal qint : std_logic:='0';
begin
P1 : process(CLK)is
begin
	if(D='1')then
		if(qint='0')then
			qint<='1';
		else
			qint<='0';
		end if;
	end if;
end process;
Q <= qint;

and this for decoder

entity NRZI_DECODER is
    Port ( CLK : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end NRZI_DECODER;

architecture Behavioral of NRZI_DECODER is
signal lastd : std_logic:='0';
begin

P1:process(CLK)is
begin
	if rising_edge(CLK) then
		if D = lastd then
			Q <= '0';
		else
			Q <= '1';
		end if;
		lastd <= D;
	end if;
end process;


end Behavioral;

Then i've created a top module where the output of encoder is the input for decoder and the clock is the same.

the result of simulation is figured below


Q of decoder doesn't move from it's logical low level. This is because, i think, the input of encoder is sampled on rising edge of clock and the input of decoder too, is it true?
How could i resolve my problem?
If the encoder is implemented on a FPGA transmitter and decoder is implemented on a FPGA receiver the problem will continue to exist?
Thanks

 

[TrickyDicky]

for your encoder, you forgot to put clk in the process.

and in your waveform everything is called D and Q - I have no idea which is the encoder and which is the decoder.

 

[franticEB]

and this is the TestBench

ENTITY nrzi_tb IS
END nrzi_tb;
 
ARCHITECTURE behavior OF nrzi_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT top_nrzi
    PORT(
         clk : IN  std_logic;
         d_in : IN  std_logic;
         q_out : OUT  std_logic
        );
    END COMPONENT;
    
   constant flag : std_logic_vector(7 downto 0):=x"7E";
   constant data : std_logic_vector(33 downto 0):="10010111" & "10100011" & "10111110" & "11111011" & "01";
   --Inputs
   signal clk : std_logic := '0';
   signal d_in : std_logic := '0';

 	--Outputs
   signal q_out : std_logic;

   -- Clock period definitions
   constant clk_period : time := 2.5 ms;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: top_nrzi PORT MAP (
          clk => clk,
          d_in => d_in,
          q_out => q_out
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '1';
		wait for clk_period/2;
		clk <= '0';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      --wait for 1 ms;	
	  
	  wait for CLK_period*5;
	  for i in 0 to 7 loop
		d_in <= flag(i); wait for CLK_period;
	  end loop;
	  for i in 0 to 7 loop
		d_in <= flag(i); wait for CLK_period;
	  end loop;
	  -----------------------------
	  for i in 0 to 33 loop
		d_in <= data(i); wait for CLK_period;
	  end loop;
	  -----------------------------
	  for i in 0 to 7 loop
		d_in <= flag(i); wait for CLK_period;
	  end loop;
	  for i in 0 to 7 loop
		d_in <= flag(i); wait for CLK_period;
	  end loop;
      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;