npn in tsmc18rf (0.18um cmos technology)

[matin-kh]

Hi every one,
In my circuit there is a npn transistor and I use 0.18um CMOS technology which I have learned before if I want to have npn transistors in CMOS technology I should use p-well. in cadence when I open a layout cell there isn't any layout view in instance in npn just symbol spectre and ... but when I put a npn transistor in schematic view and use layout XL and then gen from source I have a layout like below:



now my question is this layout is correct? because it is look like the shape which we hade in bipolar tech which emitter is in the middle and then base and then collector and i don't know the layers which is used in it for example the green one name is BJTDUMMY what is it?:shock:
if it is not correct could you help me to draw a npn transistor in this technology?
the emitter size is 2*2 and the area is 4e-12


with best regards
Matin

 

[erikl]

... now my question is this layout .. correct? because it is look like the shape which we hade in bipolar tech which emitter is in the middle and then base and then collector

Yes, it is correct. Same as in bipolar tech.

... and i don't know the layers which is used in it

I think there's a command to recognize the layer, AFAIR. If not, make one layer after the other invisible.

... for example the green one name is BJTDUMMY what is it?

I suppose this is a recognition layer for the extractor (to extract this structure as BJT, not as 2 diodes poled against each other).

the emitter size is 2*2 and the area is 4e-12

If you need a larger one, create an array of these.