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not getting synthesized

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humairalis

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again i am stuck in an issue :(
i dont know why the Line 74: Index <159> is out of range [127:0] for signal <Out01>.
pls helpp ! just the final task to achieve



module AES(In, clk, reset, Key, Out32);

input [127:0] In;
input clk,reset;
input [127:0] Key;
output [127:0] Out32;
reg [127:0] Key1= 128'hd6aa74fdd2af72fadaa678f1d6ab76fe;
reg [127:0] Key2= 128'hb692cf0b643dbdf1be9bc5006830b3fe;
reg [127:0] Key3= 128'hb6ff744ed2c2c9bf6c590cbf0469bf41;
reg [127:0] Key4= 128'h47f7f7bc95353e03f96c32bcfd058dfd;
reg [127:0] Key5= 128'h3caaa3e8a99f9deb50f3af57adf622aa;
reg [127:0] Key6= 128'h5e390f7df7a69296a7553dc10aa31f6b;
reg [127:0] Key7= 128'h14f9701ae35fe28c440adf4d4ea9c026;
reg [127:0] Key8= 128'h47438735a41c65b9e016baf4aebf7ad2;
reg [127:0] Key9= 128'h549932d1f08557681093ed9cbe2c974e;
reg [127:0] Key10= 128'h13111d7fe3944a17f307a78b4d2b30c5;
wire [127:0] Out01, Out11, Out21, Out31;
wire [127:0] Out02, Out12, Out22, Out32;
wire [127:0] Out03, Out13, Out23, Out33;
wire [127:0] Out04;
wire [127:0] Out14;
wire [127:0] Out24;
wire [127:0] Out34;
wire [127:0] Out05;
wire [127:0] Out15;
wire [127:0] Out25;
wire [127:0] Out35;
wire [127:0] Out06;
wire [127:0] Out16;
wire [127:0] Out26;
wire [127:0] Out36;
wire [127:0] Out07;
wire [127:0] Out17;
wire [127:0] Out27;
wire [127:0] Out37;
wire [127:0] Out08;
wire [127:0] Out18;
wire [127:0] Out28;
wire [127:0] Out38;
wire [127:0] Out09;
wire [127:0] Out19;
wire [127:0] Out29;
wire [127:0] Out39;
wire [127:0] Out010;
wire [127:0] Out110;
wire [127:0] Out210;

genvar i;
generate
for (i=0;i<=3;i=i+1)


AddRoundKey ark(In[i*32+:32], clk, Key[i*32+:32], Out01[i*32+:32], reset);
ShiftRow sr1(Out01[i*32+:32], clk, Out32[i*32+:32], reset);

endgenerate

endmodule

module AddRoundKey(In, clk, Key, Out, reset);

input [31:0] In;
input clk,reset;
input [31:0] Key;
output reg [31:0] Out;
always@(posedge clk)
begin
if (reset)
begin
Out=32'h00000000;
Out = In[31:0] ^ Key[31:0];
end
else;
end
endmodule


module ShiftRow(In, clk, Out,reset);

input [127:0] In;
input clk,reset;
output reg [127:0] Out;
always@(posedge clk)
begin
if (reset)
begin
Out=128'd0;

Out[127-:8] = In[127-:8];
Out[119-:8] = In[87-:8];
Out[111-:8] = In[47-:8];
Out[103-:8] = In[7-:8];
Out[95-:8] = In[95-:8];
Out[87-:8] = In[55-:8];
Out[79-:8] = In[15-:8];
Out[71-:8] = In[103-:8];
Out[63-:8] = In[63-:8];
Out[55-:8] = In[23-:8];
Out[47-:8] = In[111-:8];
Out[39-:8] = In[71-:8];

Out[31-:8] = In[31-:8];
Out[23-:8] = In[119-:8];
Out[15-:8] = In[79-:8];
Out[7-:8] = In[39-:8];

end
end
endmodule

- - - Updated - - -

humairalis said:
again i am stuck in an issue :(
i dont know why the Line 74: Index <159> is out of range [127:0] for signal <Out01>.
pls helpp ! just the final task to achieve



module AES(In, clk, reset, Key, Out32);

input [127:0] In;
input clk,reset;
input [127:0] Key;
output [127:0] Out32;
reg [127:0] Key1= 128'hd6aa74fdd2af72fadaa678f1d6ab76fe;
reg [127:0] Key2= 128'hb692cf0b643dbdf1be9bc5006830b3fe;
reg [127:0] Key3= 128'hb6ff744ed2c2c9bf6c590cbf0469bf41;
reg [127:0] Key4= 128'h47f7f7bc95353e03f96c32bcfd058dfd;
reg [127:0] Key5= 128'h3caaa3e8a99f9deb50f3af57adf622aa;
reg [127:0] Key6= 128'h5e390f7df7a69296a7553dc10aa31f6b;
reg [127:0] Key7= 128'h14f9701ae35fe28c440adf4d4ea9c026;
reg [127:0] Key8= 128'h47438735a41c65b9e016baf4aebf7ad2;
reg [127:0] Key9= 128'h549932d1f08557681093ed9cbe2c974e;
reg [127:0] Key10= 128'h13111d7fe3944a17f307a78b4d2b30c5;
wire [127:0] Out01, Out11, Out21, Out31;
wire [127:0] Out02, Out12, Out22, Out32;
wire [127:0] Out03, Out13, Out23, Out33;
wire [127:0] Out04;
wire [127:0] Out14;
wire [127:0] Out24;
wire [127:0] Out34;
wire [127:0] Out05;
wire [127:0] Out15;
wire [127:0] Out25;
wire [127:0] Out35;
wire [127:0] Out06;
wire [127:0] Out16;
wire [127:0] Out26;
wire [127:0] Out36;
wire [127:0] Out07;
wire [127:0] Out17;
wire [127:0] Out27;
wire [127:0] Out37;
wire [127:0] Out08;
wire [127:0] Out18;
wire [127:0] Out28;
wire [127:0] Out38;
wire [127:0] Out09;
wire [127:0] Out19;
wire [127:0] Out29;
wire [127:0] Out39;
wire [127:0] Out010;
wire [127:0] Out110;
wire [127:0] Out210;

genvar i;
generate
for (i=0;i<=3;i=i+1)


AddRoundKey ark(In[i*32+:32], clk, Key[i*32+:32], Out01[i*32+:32], reset);
ShiftRow sr1(Out01[i*32+:32], clk, Out32[i*32+:32], reset);

endgenerate

endmodule

module AddRoundKey(In, clk, Key, Out, reset);

input [31:0] In;
input clk,reset;
input [31:0] Key;
output reg [31:0] Out;
always@(posedge clk)
begin
if (reset)
begin
Out=32'h00000000;
Out = In[31:0] ^ Key[31:0];
end
else;
end
endmodule


module ShiftRow(In, clk, Out,reset);

input [127:0] In;
input clk,reset;
output reg [127:0] Out;
always@(posedge clk)
begin
if (reset)
begin
Out=128'd0;

Out[127-:8] = In[127-:8];
Out[119-:8] = In[87-:8];
Out[111-:8] = In[47-:8];
Out[103-:8] = In[7-:8];
Out[95-:8] = In[95-:8];
Out[87-:8] = In[55-:8];
Out[79-:8] = In[15-:8];
Out[71-:8] = In[103-:8];
Out[63-:8] = In[63-:8];
Out[55-:8] = In[23-:8];
Out[47-:8] = In[111-:8];
Out[39-:8] = In[71-:8];

Out[31-:8] = In[31-:8];
Out[23-:8] = In[119-:8];
Out[15-:8] = In[79-:8];
Out[7-:8] = In[39-:8];

end
end
endmodule
Click to expand...

dont know why whis is getting out of range
 

pls help me out with this
here i delcare a 128 bit reg with value of 128'h
but if i try fetching it in 32 bit in 4 fetches it doesnt give the accurate output



module AES(In, clk, reset, Key, Out32);

input [127:0] In;
input clk,reset;
input [127:0] Key;
output [127:0] Out32;
reg [127:0] Out31= 128'h6353e08c0960e104cd70b751bacad0e7;



wire [127:0] Out01, Out11, Out21;
wire [127:0] Out02, Out12, Out22, Out32;

genvar i;
generate
for (i=0;i<=3;i=i+1)begin




MixColumn mc1(Out31[i*32+:32], clk, Out32[i*32+:32], reset);
end

endgenerate

endmodule

module MixColumn(In, clk, Out,reset);
input [31:0] In;
input clk,reset;

output reg [31:0] Out=0;
reg [7:0] c00=0,c10=0,c20=0,c30=0;

reg [7:0] out00=0,out10=0,out20=0,out30=0;

always@(posedge clk)
begin
if (reset)
begin

c00 = In[31:24];
c20 = In[23:16];
c30 = In[15:8];
c10 = In[7:0];

case ({c00[7], c10[7]})

2'b00 : out00 = (c00 << 1) ^ (c10 << 1) ^ c10 ^ c20 ^ c30 ;
2'b01 : out00 = (c00 << 1) ^ (c10 << 1) ^ 8'h1b ^ c10 ^ c20 ^ c30 ;
2'b10 : out00 = (c00 << 1) ^ 8'h1b ^ (c10 << 1) ^ c10 ^ c20 ^ c30 ;
2'b11 : out00 = (c00 << 1) ^ 8'h1b ^ (c10 << 1) ^ 8'h1b ^ c10 ^ c20 ^ c30 ;
//default:
endcase

case ({c10[7], c20[7]})
2'b00 : out10 = c00 ^ (c10 << 1) ^ (c20 << 1) ^ c20 ^ c30 ;
2'b01 : out10 = c00 ^ (c10 << 1) ^ (c20 << 1) ^ 8'h1b ^ c20 ^ c30 ;
2'b10 : out10 = c00 ^ (c10 << 1) ^ 8'h1b ^ (c20 << 1) ^ c20 ^ c30 ;
2'b11 : out10 = c00 ^ (c10 << 1) ^ 8'h1b ^ (c20 << 1) ^ 8'h1b ^ c20 ^ c30 ;
//default:
endcase

case ({c20[7], c30[7]})
2'b00 : out20 = c00 ^ c10 ^ (c20 << 1) ^ (c30 << 1) ^ c30 ;
2'b01 : out20 = c00 ^ c10 ^ (c20 << 1) ^ (c30 << 1) ^ 8'h1b ^ c30 ;
2'b10 : out20 = c00 ^ c10 ^ (c20 << 1) ^ 8'h1b ^ (c30 << 1) ^ c30 ;
2'b11 : out20 = c00 ^ c10 ^ (c20 << 1) ^ 8'h1b ^ (c30 << 1) ^ 8'h1b ^ c30 ;
//default:
endcase

case ({c30[7], c00[7]})
2'b00 : out30 = (c00 << 1) ^ c00 ^ c10 ^ c20 ^ (c30 << 1) ;
2'b01 : out30 = (c00 << 1) ^ c00 ^ c10 ^ c20 ^ (c30 << 1) ^ 8'h1b ;
2'b10 : out30 = (c00 << 1) ^ 8'h1b ^ c00 ^ c10 ^ c20 ^ (c30 << 1) ;
2'b11 : out30 = (c00 << 1) ^ 8'h1b ^ c00 ^ c10 ^ c20 ^ (c30 << 1) ^ 8'h1b;
//default:
endcase

Out[31:24] = out00;
Out[23:16] = out10;
Out[15:8] = out20;
Out[7:0] = out30;

end

end
endmodule
 

If it doesn't work, write a testbench and simulate that sucker.

On a randomly related subject, what do you think this will do?

Code: 
wire [127:0] Out01, Out11, Out21;

More to the point, do you think Out11 and Out21 will be 128 bits wide or 1 bit wide? Have you verified that it's indeed as you think it is, and why not? Oh wait, that should have been "and if not, why not". I accidentally enable greedy evaluation. :p
 

mrflibble said:
If it doesn't work, write a testbench and simulate that sucker.

On a randomly related subject, what do you think this will do?

Code: 
wire [127:0] Out01, Out11, Out21;

More to the point, do you think Out11 and Out21 will be 128 bits wide or 1 bit wide? Have you verified that it's indeed as you think it is, and why not? Oh wait, that should have been "and if not, why not". I accidentally enable greedy evaluation. :p
Click to expand...

reg [127:0] Out31= 128'h6353e08c0960e104cd70b751bacad0e7;



wire [127:0] Out32;

genvar i;
generate
for (i=0;i<=3;i=i+1)begin




MixColumn mc1(Out31[i*32+:32], clk, Out32[i*32+:32], reset);
end

endgenerate

endmodule


I just wantd to fetch Out31 a constant 128 bit value through the vector part of module MC1 in 4 32 bit fethcing step !
 

I read that already. ;) So did you build that testbench yet? That's how people usually debug their design. ;)

Besides, a testbench is a wonderful way to realize what kind of assumptions you are making...
 

mrflibble said:
I read that already. ;) So did you build that testbench yet? That's how people usually debug their design. ;)

Besides, a testbench is a wonderful way to realize what kind of assumptions you are making...
Click to expand...

module mx_tsttt;

// Inputs
reg [127:0] In;
reg clk;
reg reset;
reg [127:0] Key;

// Outputs
wire [127:0] Out32;

// Instantiate the Unit Under Test (UUT)
AES uut (
.In(In),
.clk(clk),
.reset(reset),
.Key(Key),
.Out32(Out32)
);

always #10 clk=~clk;
always #10 reset=~reset;

initial begin
// Initialize Inputs
In = 128'hd4bf5d30e0b452aeb84111f11e2798e5;
Key =128'h11111111111111111111111111111111;
clk=1'b0;
reset=1'b0;
end

endmodule

the module output is not matching with what the encryption standard said
however if i run the MC1 module alone its giving the right output that merely means it couldnt pick up the exact bytes from 128 bit constant
if i provide it 32 bits in 4 fetches it gives the desired output but from taking input by a constant of 128 its not workin !
 

My bad, I forgot to ask for the screenshot of your sim result.

Besides, what is toggling the reset every 10 ns supposed to do? You probably want to remove that always with the reset. And then add a #100 reset = WHATEVER IT IS TO DEASSERT RESET; as the last line of your current initial statement.
 

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