#### abhiinics

##### Newbie level 3

Hello I have written the alu programm for adder, multi, divisor, subtractor.

I am getting output also but the output is not right.

Can anyone help me out by checking the ?

thanks

I am getting output also but the output is not right.

Can anyone help me out by checking the ?

Code:

```
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Entity for ALU component
-- Use this Entity for your C&A project
ENTITY ALU_E IS
PORT(
reset_n : in std_logic;
clk : in std_logic;
OperandA : in std_logic_vector(3 downto 0);
OperandB : in std_logic_vector(3 downto 0);
Operation : in std_logic_vector(2 downto 0);
Start : in std_logic;
Result_Low : out std_logic_vector(3 downto 0);
Result_High : out std_logic_vector(3 downto 0);
Ready : out std_logic;
Errorsig : out std_Logic);
END ALU_E;
architecture Behavioral_ALU of ALU_E is
signal product : std_logic_vector(7 downto 0);
signal sum, Q, R : std_logic_vector(3 downto 0);
signal diff : std_logic_vector (3 downto 0);
signal cout, b_out, err, Hold_Ready_Signal, Ready_Signal : std_logic;
component Addi is
port(
a,b : in std_logic_vector(3 downto 0);
cin : in std_logic;
cout: out std_logic;
sum : out std_logic_vector(3 downto 0));
end component;
component adderSubtractor is
port(
a,b : in std_logic_vector (3 downto 0);
bin : in std_logic;
b_out: out std_logic;
diff : out std_logic_vector (3 downto 0));
end component;
component Multi is
port(
a,b : in std_logic_vector(3 downto 0);
output : out std_logic_vector(7 downto 0));
end component;
begin
Ready <= Ready_Signal;
ADDITION: Addi
port map (OperandA, OperandB, '0', cout, sum);
Subtract: adderSubtractor
port map (OperandA, OperandB, '0', b_out, diff);
Multiplication: Multi
port map (OperandA, OperandB, product);
process (reset_n, clk, Operation)
variable counter : std_logic_vector (3 downto 0);
variable rotate_A : std_logic_vector(7 downto 0);
variable a1,b1,r,q,temp3: std_logic_vector(3 downto 0);
variable w: std_logic;
begin
if reset_n = '0' then
Result_Low <= "0000";
Result_High <= "0000";
Errorsig <= '0';
Ready_Signal <= '0';
Hold_Ready_Signal <= '0';
counter := "0000";
elsif clk'event and clk = '1' then
if(Start = '1') then -- Start calculation
counter := "0000";
case Operation is
when "001" =>
rotate_A := "0000" & OperandA;
--http://www.eng.auburn.edu/~strouce/class/elec4200/operat.pdf
while (counter < OperandB) loop
rotate_A := rotate_A(6 downto 0) & rotate_A(7);
counter := counter + "0001";
end loop;
Result_Low <= rotate_A(3 downto 0);
Result_High <= rotate_A(7 downto 4);
Errorsig <= '0';
Ready_Signal <= '1'; -- At every Ready_Signal: Calculation finished
when "010" =>
rotate_A := "0000" & OperandA;
while counter < OperandB loop
rotate_A := rotate_A(0) & rotate_A(7 downto 1);
counter := counter + "0001";
end loop;
Result_Low <= rotate_A(3 downto 0);
Result_High <= rotate_A(7 downto 4);
Errorsig <= '0';
Ready_Signal <= '1';
when "011" =>
Result_Low <= OperandA xor OperandB;
Result_High <= X"0";
Errorsig <= '0';
Ready_Signal <= '1';
when "100" =>
Result_Low <= sum;
Result_High <= "000" & cout; -- carry (cout) + LSB of the Result_High
Errorsig <= '0';
Ready_Signal <= '1';
when "101" =>
Result_Low <= diff;
Result_High <= X"0";
Errorsig <= b_out; -- Difference: Negative: Errorsig:b_out=1
Ready_Signal <= '1';
when "110" =>
Result_Low <= product(3 downto 0);
Result_High <= product(7 downto 4);
Ready_Signal <= '1';
Errorsig <= '0';
when "111" =>
if(OperandA<OperandB) then -- DIIV operation
a1:= OperandA;
b1:="0000";
Ready_Signal<='1';
elsif(OperandB="0000") then
Errorsig<='1';
elsif(OperandA>=OperandB) then
a1:= OperandA;
temp3 :="0001"; Errorsig<='0';
while (a1>=OperandB) loop
r:= a1;
q:= b1;
for I in 0 to 3 loop
a1(I):= r(I) xor OperandB(I) xor w;
w:= ((not r(I)) and OperandB(I)) or ( not(r(I)) and w)or (w and OperandB(I));
end loop;
w:= '0';
for I in 0 to 3 loop
b1(I):= w xor q(I) xor temp3(I);
w:= (q(I) and temp3(I)) or (w and (q(I) or temp3(I)));
end loop;
end loop;
Result_High<= b1;
Result_Low <= a1;
Ready_Signal<='1';
end if;
when others =>
Result_Low <="0000" ;
Result_High <="0000";
Ready_Signal <= '0';
Errorsig <= '1';
end case;
elsif Ready_Signal = '1' then --- Hold Ready_Signal for 2 clock cycles
if Hold_Ready_Signal = '1' then
Ready_Signal <= '0';
Hold_Ready_Signal <= '0';
else
Hold_Ready_Signal <='1';
end if;
end if;
end if;
end process;
end Behavioral_ALU;
```

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