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Not able to generate .tr0 .ic0 .mt0 .st0 files in Hspice

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mohitsh

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Hello sir,
Iam making a 8T Sram using Finfet and iam not able to generate .tr0 .ic0 .st0 and .mt0 files in Hspice, only .lic file is generating. Iam not able to find out the error in my program.

my program is:

Code PHP - [expand]
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*PTM
*Inverter Transient
 
.param pnch =2e16
.param ptox = 1.4e-9
.param ptsi = 8.6n 
.param ptbox = 1.4e-9
.param ppvthf0 = -0.22
.param ppvthb0 = -0.22
.param esi = 11.7
.param eox = 3.9
.param npvthf0 = 0.22
.param npvthb0 = 0.22
.temp 160
 
.include "D:\Saurabh Sior 10T SRAM\new sram\FinFET Library\32nm_finfet.PM"
.include "D:\Saurabh Sior 10T SRAM\new sram\FinFET Library\soinmos1.PM"
.include "D:\Saurabh Sior 10T SRAM\new sram\FinFET Library\soinmos2.PM"
.include "D:\Saurabh Sior 10T SRAM\new sram\FinFET Library\soipmos1.PM"
.include "D:\Saurabh Sior 10T SRAM\new sram\FinFET Library\soipmos2.PM"
 
 * --- Voltage Sources ---
Vsupply Vdd Gnd  DC 0.9
Vwbl wbl Gnd  PULSE(0 0.9 0 5p 5p 0.5n 1n)
Vwblb wblb Gnd PULSE(0.9 0 0 5p 5p 0.5n 1n) 
Vrbl rbl Gnd  PULSE(0 0.9 0 5p 5p 0.5n 1n) 
Vwwl wwl Gnd PULSE (0 0.9 0 5p 5p 0.5n 1n) 
Vrwl rwl Gnd PULSE (0 0.9 0 5p 5p 0.5n 1n) 
 
* --- Inverter Subcircuit ---
*inverter1
XMPMOS1 q qb Vdd qb dgpmos1 ldg=32nm wdg=64nm
XMNMOS1 q qb gnd qb dgnmos1 ldg=32nm wdg=64nm
 
*inverter2
XMPMOS2 qb q Vdd q dgpmos1 ldg=32nm wdg=64nm
XMNMOS2 qb q gnd q dgnmos1 ldg=32nm wdg=64nm
 
**Access tarnsistor
XMNMOS3 q wwl wbl wwl dgnmos1 ldg=32nm wdg=64nm
XMNMOS4 qb wwl wblb wwl dgnmos1 ldg=32nm wdg=64nm
XMNMOS5 a qb gnd qb dgnmos1 ldg=32nm wdg=64nm
XMNMOS6 a rwl rbl rwl dgnmos1 ldg=32nm wdg=64nm 
 
********* Simulation Settings - Analysis section *********
* --- Transient Analysis ---
 
.tran 0.1n 5n start=0n 
***instead of avg we can also write max, min or avg***
.PRINT v(q) v(qb) v(wbl) v(wblb)
********* Simulation Settings - Additional SPICE commands *********



The errors which are showing while simulating the program are:


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ERROR:(d:\saurabh sior 10t sram\new sram\8t finfet.sp:3) name:pard\ is invalid,
  abort 
 ERROR:(d:\saurabh sior 10t sram\new sram\8t finfet.sp:3) name:nowidctlpar\ is i
 nvalid, abort 
 ERROR:(d:\saurabh sior 10t sram\new sram\8t finfet.sp:3) name:f0\ is invalid, a
 bort



Please help me by proving a solution.
 
Last edited by a moderator:

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