Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Nonlinear Timing/Power lookup table for cell lib

Status
Not open for further replies.

legend03u8z

Newbie level 3
Joined
Mar 22, 2012
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,305
How Library Compiler determine the index interval for a 2-D lookup table?
the variables listed in x-axis,and y-axis are not normally distributed.

Thanks
 

LibraryCompiler does not determine the index (interval and count of index). It just convert your .lib file into .db file.

It is library designer (engineer) responsibility to determine number of indexes. It may be done manually (by tunning some spice simulations) or automatically (some library characterization tools may do it). Number and interval of indexes must provide good correlation between StaticTimingAnalysis (based on .lib file) and spice simulation (based on transistor netlist, which mimic the real chip timing).

In the begining of index set, the interval is smaller, then it is increased. It is because, in case of small output pin capacitance, the cell delay (as well as transition) is not linearly increased with capacitance increasing. So, we need to have more indexes in this area.
 

LibraryCompiler does not determine the index (interval and count of index). It just convert your .lib file into .db file.

It is library designer (engineer) responsibility to determine number of indexes. It may be done manually (by tunning some spice simulations) or automatically (some library characterization tools may do it). Number and interval of indexes must provide good correlation between StaticTimingAnalysis (based on .lib file) and spice simulation (based on transistor netlist, which mimic the real chip timing).

In the begining of index set, the interval is smaller, then it is increased. It is because, in case of small output pin capacitance, the cell delay (as well as transition) is not linearly increased with capacitance increasing. So, we need to have more indexes in this area.

First of all thank you very much!

Currently, I'm looking for how the building-lib software work. I have found a equation to generate the number and value of the breakpoints for LUT.
Refered to SiliconSmart userguide, the index can be calculated by = smallest_slew+a(largest_slew-smallest_slew), and a=(I^2.5+I^1.75)/(Imax^2.5+Imax^1.75), where integer I varies from 0 to Imax, and Imax=numsteps_slew-1.

I have done a test based this equation, the resulting indexs are corresponding to a generated .lib file
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top