non-resettable flip-flop

[giri_lp]

Hi,
I have a generic question. Where do we use Non-resettable flip-flop in the design?

What are the advantages of Non-resettable flip-flop
-Giri

 

[D.A.(Tony)Stewart]

All Flip Flops are State Machine memory cells. Some do not need the added complexity of reset and are only edge triggered latches. But then Reset ensures a power on control initial condition if required.

 

[jbeniston]

Register files.

The advantages are they are smaller and sometimes faster and/or use less power.

 

[giri_lp]

Thanks jbenitson...

 

[artmalik]

Non-resettable flops are used everywhere.....!!! it is highest usage flop in any design. The resettable flops have limited usage. The technical advantage of resettable flop is that you can reach "known" state in a finite machine using a single transition on the reset pin else you might have to go through multiple cycles on the clock to reach a known state. This is mainly needed when you power on the chip. There is trade off between "no of cycles needed" to the extra area that one has to pay for resettable flops.

 

[jt_eaton]

Non-resettable flops are used everywhere.....!!! it is highest usage flop in any design. The resettable flops have limited usage. The technical advantage of resettable flop is that you can reach "known" state in a finite machine using a single transition on the reset pin else you might have to go through multiple cycles on the clock to reach a known state. This is mainly needed when you power on the chip. There is trade off between "no of cycles needed" to the extra area that one has to pay for resettable flops.

There is also a trade off with verification. When you choose a Non-resettable flop then you must also verify that the design will work under any startup condition. If you mess up and choose a resettable flop when a non-resettable would have worked then you have an almost unmeasureable increase in area or power but do not need to verify any other startup conditions.

If you mess up and choose a non-resettable flop when you really needed a resettable one then it will cost you $1,200,000 for a new set of masks.

The extra cost of using non-resettable flops does not justify the risk. Only use non-resettable flops if you are absolutely sure that they will work under all startup conditions.

 

[dick_freebird]

Yeah, non-resettable FFs are a real problem both in getting
simulations to run, and in test development - without a
chip scale reset you end up needing to figure out a preamble
that works every time on every unit under every corner
condition. Your test engineer will hate you and your boss
will wonder why you have so many problems getting anything
done.

 

[sharath666]

Non-resettable flops are used everywhere.....!!! it is highest usage flop in any design. The resettable flops have limited usage.

Hi artmalik. Could you give me examples of such non resetttable flops. Take a generic digital controller as an example.

 

[ads-ee]

Hi artmalik. Could you give me examples of such non resetttable flops. Take a generic digital controller as an example.

The only way artmalik would think this way is if all they work on is pure datapath designs that have very little control logic. If all you are doing is something like a running average or filtering some signal then you don't need any resets anywhere except perhaps in some specific control signal or FSM. If they taped out a design with an FSM with a dead state and that FSM doesn't have a reset. Well I can see some very ugly problem reports coming back from the field...e.g. "You're POS device locked up on powerup and we had to cycle power a few time before it started working. If you don't fix this we are buying from company xyz instead of you guys."

 

[jbeniston]

There is also a trade off with verification. When you choose a Non-resettable flop then you must also verify that the design will work under any startup condition.

Which isn't hard, as it's an X in simulation.

 

[jt_eaton]

Which isn't hard, as it's an X in simulation.

X's in simulation happen to be really hard to deal with. Suppose you have rtl code for an inverter:

always@(*)
if(A) B= 0;
else B=1;


If A is X then B should also be an X but instead becomes a 1. In silicon if the A value of X turned out to be a 1 then we have a simulation synthesys mismatch.

You can also have logic that is capable of resolving an X but because verilog is pessimistic it is unable to figure that out. In other words if A equals 0 or 1 then it can figure out B but if A equals X then it assign X to B.

The only way to handle an X is to put all nodes into a known state at the start of your simulation and run it until any node goes to an X. That tells you that you have an error and you cannot continue to run until you fix it.

 

[jbeniston]

Ideally you want the second form, that way Xs propagate, and you can easily see where you've used an uninitialized value. (See here for some interesting points **broken link removed**, such as not using ifs in combinational logic, for this reason). It's by no means fool proof, but useful if you really need those area and power savings. That may not be the case in every design