Non-constant part select error in Verilog!

[rocking]

verilog variable part select

Hi!

I'm trying to execute the following statement:

var[119-i:112-i] <= temp;

I get an error that says non-constant part select index.

What I am trying to do is that I have a 120 bit register called var. I'm getting an 8 bit value called temp from combinational logic and I want to assign it to the 1st 8 MSBs of var i.e. from var[119:112]. Then for the second value of temp, I want to assign it to var[111:104] and so on till var is filled.

any help would be greatly appreciated!

Thanks

 

[it_boy]

verilog part select

this should work..

wire [127:0] var;
reg [7:0] a [15:0];
reg [3:0] i;

assign var = {a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8],
a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]};

always @ (posedge clk)
begin
a <= temp;
i <= i + 1'b1;
end

 

[rocking]

part select in verilog

This proved very helpful!
Thanks!