non blocking assignment in verilog

[qne]

hi .
i m verilog beginner . i need to know some basic questions , hope u all help me ..

=> what is difference between these two inst.
a: reg[3:0] b: wire[3:0]
what is the sequence of this code?
always @(posedge clk)
dff1 <= f(x);
assign fsm_in = f(dff1);
assign fsm_out = fsm_state;
always @(fsm_in)
fsm_state <= g(fsm_in);
i will really appericite if someone put here some examples that illustrate the concept of non blocking assignments.

regards..

 

[cks3976]

A. Both WIRE and REG are Verilog data types. WIRE is used to connect two points while REG is used for storing values.

Blocking assignment executes the code (data flow) sequentially inside a "BEGIN-END" module, meaning for a blocking assignment statement to be executed, the previous condition must be successfully asserted. A blocking assignment is done using "=" . On the other hand non-blocking assignment does a parallel data execution, given a master condition (in this case POSEDGE of CLK) is executed the non-blocking assignment (<=) assigns the given data in parallel to other sequential elements.

In the above code, f(x) is assigned to DFF1 on the Positive edge of the clock. And later the state assignment to the FSM takes place as per the code flow.

Hope this help..

 

[optimuz]

Adding some more points to what cks3976 said.

1.About REG and WIRE.
Both are verilog data types. If you want to assign or force some values to a particular variable inside your verilog code, you should use it as REG data type. Because REG has the capability of storing the value, but WIRE dint. So when you are doing behavioural modelling(using "always/initial" keyword), and you are assigning something to your output port, you should declare it as REG data type. Where as in Continous assignment(using "assign" keyword) you dont have to make it as REG.
WIRE should be always driven in order to retain the value on the WIRE. So it is same as the wire connection in basic electronics.

2. Blocking and Non Blocking
Blocking mode

always @ (*)
begin
a=1;
b=a;
c=b;
end

When the compiler see this code. It will first execute the "a=1". After that "b=a". As "a" has the value 1 now, it will be carried to "b" and the by next statement to "c" too.

Non Blocking mode

always @ (*)
begin
a<=1;
b<=a;
c<=b;
end

Here the compiler sees the code parallelly inside the always block. So it estimates the value of LHS first and store it in a memory. So first compiler schedule 1 to "a". Then as "a" is having unkown value(z), compiler schedule z to b, and as "b" is also unkown , again z to "c". So after these scheduling is done, the values are copied.
And again if the always block is activated, now the value of 1 is scheduled to "a", "1" to "b" , and z to "c".

Hope this is helpful
Optimuz

 

[FvM]

Now the $1000 question. Will you observe any differences in the actual output of both example codes, as given here?

 

[cks3976]

Aah.... FvM, nice observation...well, actually there is no difference in execution sequence here . Better example would have been the code in original post by qne

 

[optimuz]

Now the $1000 question. Will you observe any differences in the actual output of both example codes, as given here?

I hope the in NBA it needs three trigerring for the sensitivity list to get the same output as the blocking. Or else for better simulation view, that * can be replaced by a "posedge clk".

 

[FvM]

The non-blocking example needs in fact three delta cycles for the final result. My question was however, if it causes a behavioral difference. It's no the case (for the present code) with always @(*), which models combinational logic, but of course matters for a clock synchronous always block.

 

[optimuz]

The non-blocking example needs in fact three delta cycles for the final result. My question was however, if it causes a behavioral difference. It's no the case (for the present code) with always @(*), which models combinational logic, but of course matters for a clock synchronous always block.

Yes ofcourse I agree with u FvM. Thanks for finding it out for me.

 

[qne]

very nice all of u ...
lets take another example ..

---

Code Verilog - [expand]
1
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5
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initial 
begin 
        a= 0;
        b= #10  1;
        c= #5    0;
        d = #20   {a,b,c};
end

---

=> what are the final values of a,b,c,d.
=> what are the final values with non blocking assignment..
plz comment on it . i m unable to understand last statement i.e d = #20 {a,b,c}: its concatenation or something else?

 

[mrflibble]

its concatenation or something else?

You got it. It's concatenation. See Verilog Operators Part-II for some examples.

 

[Sink0]

Hmm i will take some advantage of this thread and ask a question about verilog. So far the way that i could find to have a very well controlled output is to just use blocking assignment on "always @ (*)" leading to a combinatorial logic, and just use non-blocking assignment on clocked logic (always @ (posedge clk)). Following this rule i pretty much can control my critical timing and behavior of my logic. My question is, am i being too cautious? What advantages i would have following any other coding style. e.g using blocking assignments on a clocked logic or non-blocking assignments on a always @ (*)?

Thank you!

 

[FvM]

The suggested usage of blocking and non-blocking assignments is in accordance common practice, I think. You can refer e.g. to the Verilog coding guidelines in the famous Cummings paper https://www.edaboard.com/threads/175727/#post737345.

In a addition, I see a reasonable purpose for blocking statements, mixed with non-blocking in sequential (clock edge sensitive) always blocks:
- in iteration constructs (e.g. for loops)
- to calculate intermediate results within the same clock cycle, that are used as input to other expressions

It should be clear, that in both cases longer register-to-register delays are created. You have to decide about it in a trade-off between design clock frequency and complexity of non-pipelined logic.