Hi;
the answer to your question is a definite YES.
It is important to have the address bus free of noise and glitches, which can cause inadvertent read operations.
Yes, if the noise occurs on the address, data and/or control lines the data will be corrupted. If the noise on the power supply temporarily "remove" the power to the RAM there may be data corruption. In both cases the noise amplitude must be around the logic level for the specific RAM
is the product used for any critical application, then there are various error detection and error correction techniques to be implemented in order to minimise this...
Slow March test, CRC,, double inverted storage techniques are very oftenly used....
Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.
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And how can i test my circuit for its noise immunity? or how can i test my circuit for measuring error caused by noise?
is there any standard for such testing?