mishrashashi
Advanced Member level 4
hi all,
I have a silly problem. I am using Allegro SI tool for DDR2 Signals. For noise margin i found the theoretical values
Noise Margin (High)= VNH = VOH (Min) - VIH (Min) = 2.97-1.025= 1.945 V
Noise Margin (Low)= VNL = VIL (Max) - VOL (Max) = 0.775- 0.4 = 0.375 V
but simulation result gives the range of 5.475 V to 6545 V. What will be effect on signal transmission. If these values are not good for the design,please suggest me solution to reduce these values.
Thanks in advance
I have a silly problem. I am using Allegro SI tool for DDR2 Signals. For noise margin i found the theoretical values
Noise Margin (High)= VNH = VOH (Min) - VIH (Min) = 2.97-1.025= 1.945 V
Noise Margin (Low)= VNL = VIL (Max) - VOL (Max) = 0.775- 0.4 = 0.375 V
but simulation result gives the range of 5.475 V to 6545 V. What will be effect on signal transmission. If these values are not good for the design,please suggest me solution to reduce these values.
Thanks in advance