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Noise interview question

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yolande_yj

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2 NMOS connected as current mirror with 1:5 ratio. 1 being the source side and 5 being the load side.
Question: which one has more contribution to the load and why?

My answer was the 1, or source side NMOS. Any noise will copy 5 times to the load.
The interviewer gave me a hint that the thermal noise is 4KTrGm, ask me if I would like to change my mine.
I said Gm is proportional to sqrt(Ids), so the load side NMOS contributes sqrt(5) of noise, still less than x5 from the source side.


after the interview I think a little more, the thermal noise is proportional to sqrt(Ids*W/L), so does it mean the load side NMOS also contribute sqrt(5*5)=5x noise, same as the source NMOS?
what do you think?
 

I would go with your first answer too. In a current mirror, they have the same effective gate voltage, so (arguably) simpler to use gm = 2 I / Veff. This would be my argument:

A transistor has 4kT r gm of noise current PSD, means from the secondary side you have

Is^2(f) = 4kT r gms = 4kT r (2 * 5 * I / Veff)​

The noise current on the input would be

Ip^2(f) = 4kT r gmp = 4 kT r (2 * I / Veff)​

and on the gates, the noise voltage PSD would be

Vg^2(f) = 4kT r gmp / gmp^2 (assuming gds << gm) = 4kT r / gmp​

Which is transferred to output as per

4kT r / gmp * gms^2 = 4kT r gms^2/gmp = 4kT r gms * (gms/gmp) = Is^2(f) * (2*5*I/Veff) / (2*I/Veff) = 5 Is^2(f)​

However, in this hypothetical question the bandwidth limitation was not mentioned at all. The primary transistor, for example, would potentially see a larger capacitive load than the secondary, etc.
 

On the load side you have five 1x transistors in parallel, each having the same gm as the transistor on the source side. We can consider these 5 parallel transistors as uncorrelated for noise purposes. So, the noise PSD current from them is 5x4kTrgm. The PSD of the source transistor is 4kTrgm and is multiplied by 5^2 contributing to the output noise PSD. So, obviously the source transistor contributes 5x more noise power.
 

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