dIout = -dVin*(gmNMOS + gmPMOS) - dVdd*gmPMOS
Vout/Vsupply = (gmP + gdsP) / (gdsN + gdsP).
I presume you are analyzing the inverter in linear mode, with both transistors in saturation. The output current is the sum of NMOS and PMOS drain current then. For the shorted case Rload << Rout you get
Code:dIout = -dVin*(gmNMOS + gmPMOS) - dVdd*gmPMOS
Means the PMOS transistor generates a strong power supply effect, without considering output resistance at all. Statement 2 is in so far misleading I think.
frankrose has elaborated about it in the meantime. It's the same as Vsupply*gmP in the post #8 scheme. As mentioned before, this term is actually the dominant one in poor inverter power supply rejection.How do you obtain the extra term "dVdd*gmPMOS" ?
AC analysis basically, but AC analysis of a non-linear circuit depends on a correct DC operation point.Which method (DC op point simulation / AC analysis) is more suitable in output impedance measurement of any circuit (not just CMOS inverter) ?
Sweep the input DC level and perform an AC analysis for each DC level.
Yes.The Rbias has to be large as well
The inverter is self biased, don't set Vgs manually.Vgs set to Vdd/2 ?
Each capacitance should be large compared to the connected node impedance.
use a switch to set the DC point at the input based on the output such that they are more or less the same
If you do not use the C_large at the input, you get somewhat strange results. You want to AC-shunt the input to ground quite quickly in the frequency domain, such that the resistance can be ignored.
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