dick_freebird;. I'd infer that
the FET is PMOS given the trigger network.[/QUOTE said:
Thanks. I forget that there is a inverter before M1.
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If there is a large positive voltage spike on the input pad , the diode d1 conducts, then current goes into vdd. Whether power supply vdd is also has a positve voltage spike caused by the input positive spike?
If vdd has no positive spike from the input pad, then the gate of M1 is 0, M1 is off, the discharge current can't go through M1.
So the input positive spike can lead to the vdd positive spike, right? Thanks.